Issued Patents 2004
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833625 | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect | Pin-Chin Connie Wang | 2004-12-21 |
| 6770559 | Method of forming wiring by implantation of seed layer material | Ercan Adem, Joffre F. Bernard | 2004-08-03 |
| 6768204 | Self-aligned conductive plugs in a semiconductor device | Todd P. Lukanc, Darrell M. Erb | 2004-07-27 |
| 6767827 | Method for forming dual inlaid structures for IC interconnections | Lynne A. Okada, James Kai | 2004-07-27 |
| 6756300 | Method for forming dual damascene interconnect structure | Jerry Cheng, Lynne A. Okada, Minh Quoc Tran, Lu You | 2004-06-29 |
| 6756303 | Diffusion barrier and method for its production | Darrell M. Erb | 2004-06-29 |
| 6740566 | Ultra-thin resist shallow trench process using high selectivity nitride etch | Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Khanh B. Nguyen, Chih-Yuh Yang | 2004-05-25 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof | Lu You, Lynne A. Okada | 2004-03-02 |
| 6689684 | Cu damascene interconnections using barrier/capping layer | Lu You, Richard J. Huang | 2004-02-10 |
| 6677679 | Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers | Lu You, Dawn Hopper | 2004-01-13 |