Issued Patents 2002
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495472 | Method for avoiding erosion of conductor structure during removing etching residues | Chih-Ning Wu | 2002-12-17 |
| 6492250 | Polycide gate structure and method of manufacture | Hidetake Horiuch | 2002-12-10 |
| 6488807 | Magnetic confinement in a plasma reactor having an RF bias electrode | Kenneth S. Collins, Jerry Wong, Jeffrey Marks, Peter Keswick, David W. Groechel +7 more | 2002-12-03 |
| 6461904 | Structure and method for making a notched transistor with spacers | Bo Jin | 2002-10-08 |
| 6453915 | Post polycide gate etching cleaning method | Chih-Ning Wu | 2002-09-24 |
| 6444137 | Method for processing substrates using gaseous silicon scavenger | Kenneth S. Collins, Jerry Wong, Jeffrey Marks, Peter Keswick, David W. Groechel | 2002-09-03 |
| 6440866 | Plasma reactor with heated source of a polymer-hardening precursor material | Kenneth S. Collins, Michael R. Rice, David W. Groechel, Gerald Yin, Jon Mohn +5 more | 2002-08-27 |
| 6440873 | Post metal etch cleaning method | Chih-Ning Wu | 2002-08-27 |
| 6426298 | Method of patterning a dual damascene | Tong-Yu Chen | 2002-07-30 |
| 6406640 | Plasma etching method | Usha Raghuram, Kimberley A. Kaufman, Daniel Arnzen, James E. Nulty | 2002-06-18 |
| 6403488 | Selective SAC etch process | Dan Arnzen, Jim Nulty | 2002-06-11 |
| 6399514 | High temperature silicon surface providing high selectivity in an oxide etch process | Jeffrey Marks, Jerry Wong, David W. Groechel, Peter Keswick | 2002-06-04 |
| 6368974 | Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching | Ming-Huan Tsai | 2002-04-09 |
| 6355568 | Cleaning method for copper dual damascene process | Sung-Hsiung Wang | 2002-03-12 |
| 6352938 | Method of removing photoresist and reducing native oxide in dual damascene copper process | Tong-Yu Chen, Hsi-Ta Chuang | 2002-03-05 |