Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6989604 | Conformal barrier liner in an integrated circuit interconnect | Christy Mei-Chu Woo, Minh Van Ngo, Steven C. Avanzino | 2006-01-24 |
| 6972985 | Memory element having islands | Darrell Rinerson, Christophe J. Chevallier, Philip Swab, Steve Kuo-Ren Hsia, Steven W. Longcor | 2005-12-06 |
| 6869878 | Method of forming a selective barrier layer using a sacrificial layer | Ercan Adem, Darrell M. Erb, Suzette K. Pangrle | 2005-03-22 |
| 6836017 | Protection of low-k ILD during damascene processing with thin liner | Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, Suzette K. Pangrle | 2004-12-28 |
| 6822437 | Interconnect test structure with slotted feeder lines to prevent stress-induced voids | Christine Hau-Riege, Amit P. Marathe | 2004-11-23 |
| 6727592 | Copper interconnect with improved barrier layer | Christy Mei-Chu Woo, Darrell M. Erb, Amit P. Marathe | 2004-04-27 |
| 6723635 | Protection low-k ILD during damascene processing with thin liner | Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, Suzette K. Pangrle | 2004-04-20 |
| 6657304 | Conformal barrier liner in an integrated circuit interconnect | Christy Mei-Chu Woo, Minh Van Ngo, Steven C. Avanzino | 2003-12-02 |
| 6617176 | METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED | Pin-Chin Connie Wang, Christy Mei-Chu Woo, Paul R. Besser | 2003-09-09 |
| 6525428 | Graded low-k middle-etch stop layer for dual-inlaid patterning | Minh Van Ngo, Steven C. Avanzino, Christy Mei-Chu Woo | 2003-02-25 |
| 5597458 | Method for producing alloy films using cold sputter deposition process | Darin A. Chan, Paul R. Besser | 1997-01-28 |