| 12327117 |
System, apparatus and methods for performant read and write of processor state information responsive to list instructions |
Kameswar Subramaniam, Jason W. Brandt, Christopher Russell, Gilbert Neiger |
2025-06-10 |
|
| 12020031 |
Methods, apparatus, and instructions for user-level thread suspension |
Michael Mishaeli, Jason W. Brandt, Gilbert Neiger, Asit K. Mallick, Rajesh M. Sankaran +3 more |
2024-06-25 |
$22,163,000 |
| 11683310 |
Protecting supervisor mode information |
Barry E. Huntley, Gilbert Neiger, Asit K. Mallick, Adriaan Van De Ven, Scott Dion Rodgers |
2023-06-20 |
$18,411,000 |
| 11656873 |
Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture |
Vedvyas Shanbhogue, Gilbert Neiger, Deepak Gupta |
2023-05-23 |
$11,397,000 |
| 11243769 |
Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture |
Vedvyas Shanbhogue, Gilbert Neiger, Deepak Gupta |
2022-02-08 |
$27,206,000 |
| 11023233 |
Methods, apparatus, and instructions for user level thread suspension |
Michael Mishaeli, Jason W. Brandt, Gilbert Neiger, Asit K. Mallick, Rajesh M. Sankaran +3 more |
2021-06-01 |
$35,542,000 |
| 11019061 |
Protecting supervisor mode information |
Barry E. Huntley, Gilbert Neiger, Asit K. Mallick, Adriaan Van De Ven, Scott Dion Rodgers |
2021-05-25 |
$32,857,000 |
| 10999284 |
Protecting supervisor mode information |
Barry E. Huntley, Gilbert Neiger, Asit K. Mallick, Adriaan Van De Ven, Scott Dion Rodgers |
2021-05-04 |
$37,420,000 |
| 10135825 |
Protecting supervisor mode information |
Barry E. Huntley, Gilbert Neiger, Asit K. Mallick, Adriaan Van De Ven, Scott Dion Rodgers |
2018-11-20 |
$25,900,000 |
| 9740644 |
Avoiding premature enabling of nonmaskable interrupts when returning from exceptions |
Gilbert Neiger |
2017-08-22 |
$8,061,000 |
| 9411600 |
Instructions and logic to provide memory access key protection functionality |
Martin G. Dixon |
2016-08-09 |
$12,367,000 |
| 9411601 |
Flexible bootstrap code architecture |
Vincent J. Zimmer, Michael A. Rothman, David Estrada, Nicholas J. Yoke, Gopinatth Selvaraje |
2016-08-09 |
$12,367,000 |
| 9116729 |
Handling of binary translated self modifying code and cross modifying code |
Nirajan L. Cooray, David Keppel, Naveen Kumar, Ori Lempel, Michael Neilly +2 more |
2015-08-25 |
$14,120,000 |
| 8924648 |
Method and system for caching attribute data for matching attributes with physical addresses |
Guillermo J. Rozas, Alexander Klaiber, John Banning |
2014-12-30 |
|
| 8806247 |
Adaptive power control |
Sameer Halepete, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman +2 more |
2014-08-12 |
|
| 8566564 |
Method and system for caching attribute data for matching attributes with physical addresses |
Guillermo J. Rozas, Alexander Klaiber, John Banning |
2013-10-22 |
|
| 8566627 |
Adaptive power control |
Sameer Halepete, Zongjian Chen, Godfrey P. D'Souza, Marc Fleischmann, Keith Klayman +2 more |
2013-10-22 |
|
| 8549211 |
Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine |
— |
2013-10-01 |
|
| 8458437 |
Supporting multiple byte order formats in a computer system |
— |
2013-06-04 |
|
| 8438548 |
Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version |
John Banning, Robert Bedicheck, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds +1 more |
2013-05-07 |
|
| 8370604 |
Method and system for caching attribute data for matching attributes with physical addresses |
Guillermo J. Rozas, Alexander Klaiber, John Banning |
2013-02-05 |
|
| 8341329 |
Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine |
— |
2012-12-25 |
|
| 8335930 |
Architecture, system, and method for operating on encrypted and/or hidden information |
Richard C. Johnson, Andrew Morgan, Linus Torvalds |
2012-12-18 |
|
| 8239656 |
System and method for identifying TLB entries associated with a physical address of a specified range |
Guillermo J. Rozas, Alexander Klaiber, David Dunn |
2012-08-07 |
|
| 8156308 |
Supporting multiple byte order formats in a computer system |
— |
2012-04-10 |
|
