Issued Patents All Time
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182602 | Provisioning DPU management operating systems using firmware capsules | Andrei Warkentin, Karthik Ramachandra, Timothy P. Mann, Jared McNeill, Sunil Kotian +1 more | 2024-12-31 |
| 11995459 | Memory copy during virtual machine migration in a virtualized computing system | Arunachalam Ramanathan, Yanlei Zhao, Anurekh Saxena, Yury Baskakov, Jeffrey W. Sheldon +2 more | 2024-05-28 |
| 11893410 | Secure storage of workload attestation reports in a virtualized and clustered computer system | Abhishek Srivastava, Jesse Pool, Adrian Drzewiecki | 2024-02-06 |
| 11886223 | Leveraging hardware-based attestation to grant workloads access to confidential data | Abhishek Srivastava, Jesse Pool, Adrian Drzewiecki | 2024-01-30 |
| 11799670 | Secure end-to-end deployment of workloads in a virtualized environment using hardware-based attestation | Abhishek Srivastava, Jesse Pool, Adrian Drzewiecki | 2023-10-24 |
| 11709700 | Provisioning identity certificates using hardware-based secure attestation in a virtualized and clustered computer system | Abhishek Srivastava, Jesse Pool, Adrian Drzewiecki | 2023-07-25 |
| 11379385 | Techniques for protecting memory pages of a virtual computing instance | Alok Nemchand Kataria, Wei Xu, Radu Rugina, Jeffrey W. Sheldon, James S. Mattson, Jr. +1 more | 2022-07-05 |
| 11182183 | Workload placement using conflict cost | Xunjia Lu, Haoqiang Zheng, Fred Jacobs | 2021-11-23 |
| 10768962 | Emulating mode-based execute control for memory pages in virtualized computing systems | Doug Covelli | 2020-09-08 |
| 10678909 | Securely supporting a global view of system memory in a multi-processor system | Alok Nemchand Kataria, Doug Covelli, Jeffrey W. Sheldon, Frederick Joseph Jacobs | 2020-06-09 |
| 10592267 | Tree structure for storing monitored memory page data | Alok Nemchand Kataria, Wei Xu, Jeffrey W. Sheldon | 2020-03-17 |
| 10324725 | Fault detection in instruction translations | Nathan Tuck, Ross Segelken, Madhu Swarna | 2019-06-18 |
| 10241810 | Instruction-optimizing processor with branch-count table in hardware | Rupert Brauch, Madhu Swarna, Ross Segelken, Ben Hertzberg | 2019-03-26 |
| 10146545 | Translation address cache for a microprocessor | Ross Segelken, Alex Klaiber, Nathan Tuck | 2018-12-04 |
| 10120738 | Hypervisor techniques for performing non-faulting reads in virtual machines | Radu Rugina, Jeffrey W. Sheldon, James S. Mattson, Jr. | 2018-11-06 |
| 10108424 | Profiling code portions to generate translations | Nathan Tuck, Alexander Klaiber, Ross Segelken, Ben Hertzberg, Rupert Brauch +3 more | 2018-10-23 |
| 9823931 | Queued instruction re-dispatch after runahead | Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +6 more | 2017-11-21 |
| 9331869 | Input/output request packet handling techniques by a device specific kernel mode driver | Timothy Zhu, Randy Spurlock, Thomas Spacie | 2016-05-03 |
| 9135596 | System and method to allocate resources in service organizations with non-linear workflows | — | 2015-09-15 |
| 8661265 | Processor modifications to increase computer system security | — | 2014-02-25 |
| 8607025 | Data structure for enforcing consistent per-physical page cacheability attributes | Alexander Klaiber | 2013-12-10 |
| 8473727 | History based pipelined branch prediction | John Banning | 2013-06-25 |
| 8239656 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, Alexander Klaiber, H. Peter Anvin | 2012-08-07 |
| 8117421 | Data structure for enforcing consistent per-physical page cacheability attributes | Alexander Klaiber | 2012-02-14 |
| 8078853 | Explicit control of speculation | H. Peter Anvin | 2011-12-13 |