| 12462323 |
Shared dynamic buffer in image signal processor |
Ashwanth Subramanian, Damon W. Finney, Marc A. Schaub, Albert Kuo, Richard L. Schober |
2025-11-04 |
|
| 10628160 |
Selective poisoning of data during runahead |
Magnus Ekman, James van Zoeren |
2020-04-21 |
$727,186,000 |
| 10001996 |
Selective poisoning of data during runahead |
Magnus Ekman, James van Zoeren |
2018-06-19 |
$289,327,000 |
| 9891972 |
Lazy runahead operation for a microprocessor |
Magnus Ekman, Ross Segelken, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren +4 more |
2018-02-13 |
$344,474,000 |
| 9875105 |
Checkpointed buffer for re-entry from runahead |
Guillermo J. Rozas, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken +2 more |
2018-01-23 |
$437,819,000 |
| 9823931 |
Queued instruction re-dispatch after runahead |
Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Brad Hoyt, Sridharan Ramakrishnan +6 more |
2017-11-21 |
$112,129,000 |
| 9740553 |
Managing potentially invalid results during runahead |
Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Brad Hoyt +5 more |
2017-08-22 |
$236,127,000 |
| 9645929 |
Speculative permission acquisition for shared memory |
James van Zoeren, Alexander Klaiber, Guillermo J. Rozas |
2017-05-09 |
$221,760,000 |
| 9632976 |
Lazy runahead operation for a microprocessor |
Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Brad Hoyt, Sridharan Ramakrishnan +4 more |
2017-04-25 |
$164,591,000 |
| 9081563 |
Method and apparatus for enhancing scheduling in an advanced microprocessor |
Guillermo J. Rozas, Godfrey P. D'Souza, Charles R. Price |
2015-07-14 |
|
| 8516224 |
Pipeline replay support for multicycle operations |
Brett W. Coon, Godfrey P. D'Souza |
2013-08-20 |
|
| 8209517 |
Method and apparatus for enhancing scheduling in an advanced microprocessor |
Guillermo J. Rozas, Godfrey P. D'Souza, Charles R. Price |
2012-06-26 |
|
| 8117423 |
Pipeline replay support for multicycle operations |
Brett W. Coon, Godfrey P. D'Souza |
2012-02-14 |
|
| 7886135 |
Pipeline replay support for unaligned memory operations |
Brett W. Coon, Godfrey P. D'Souza |
2011-02-08 |
|
| 7873793 |
Supporting speculative modification in a data cache |
Guillermo J. Rozas, Alexander Klaiber, David Dunn, Lacky V. Shah |
2011-01-18 |
|
| 7725656 |
Braided set associative caching techniques |
Guillermo J. Rozas, Alexander Klaiber, Robert P. Masleid, John Banning, James Van Zoeren |
2010-05-25 |
|
| 7685403 |
Pipeline replay support for multi-cycle operations |
Brett W. Coon, Godfrey P. D'Souza |
2010-03-23 |
|
| 7606979 |
Method and system for conservatively managing store capacity available to a processor issuing stores |
Guillermo J. Rozas, Alexander Klaiber, David Dunn, Lacky V. Shah |
2009-10-20 |
|
| 7225299 |
Supporting speculative modification in a data cache |
Guillermo J. Rozas, Alexander Klaiber, David Dunn, Lacky V. Shah |
2007-05-29 |
$1,082,000 |
| 7149851 |
Method and system for conservatively managing store capacity available to a processor issuing stores |
Guillermo J. Rozas, Alexander Klaiber, David Dunn, Lacky V. Shah |
2006-12-12 |
$1,784,000 |
| 7134001 |
Pipeline replay support for unaligned memory operations |
Brett W. Coon, Godfrey P. D'Souza |
2006-11-07 |
$3,821,000 |
| 7089404 |
Method and apparatus for enhancing scheduling in an advanced microprocessor |
Guillermo J. Rozas, Godfrey P. D'Souza, Charles R. Price |
2006-08-08 |
$2,561,000 |
| 6728865 |
Pipeline replay support for unaligned memory operations |
Brett W. Coon, Godfrey P. D'Souza |
2004-04-27 |
$11,443,000 |
| 6604188 |
Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction |
Brett W. Coon, Godfrey P. D'Souza |
2003-08-05 |
$4,459,000 |
| 6571316 |
Cache memory array for multiple address spaces |
Godfrey P. D'Souza |
2003-05-27 |
$4,163,000 |
