BH

Bruce Holmer

NV NVIDIA: 5 patents #1,388 of 7,811Top 20%
TL Tera Logic: 3 patents #6 of 20Top 30%
ZO Zoran: 2 patents #43 of 200Top 25%
Infineon Technologies Ag: 2 patents #91 of 446Top 25%
CH Csr Technology Holdings: 1 patents #107 of 236Top 50%
SA Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
Overall (All Time): #350,236 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9740553 Managing potentially invalid results during runahead Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +5 more 2017-08-22
8902241 Interactive set-top box having a unified memory architecture David Auld, Hong-Jyeh Jason Huang, Gerard K. Yeh 2014-12-02
7986326 Interactive set-top box having a unified memory architecture David Auld, Hong-Jyeh Jason Huang, Gerard K. Yeh 2011-07-26
7710424 Method and system for a texture-aware virtual memory subsystem Edward A. Hutchins, James T. Battle 2010-05-04
7688324 Interactive set-top box having a unified memory architecture David Auld, Hong-Jyeh Jason Huang, Gerard K. Yeh 2010-03-30
7418606 High quality and high performance three-dimensional graphics architecture for portable handheld devices 2008-08-26
7328358 High quality and high performance three-dimensional graphics architecture for portable handheld devices 2008-02-05
7313710 High quality and high performance three-dimensional graphics architecture for portable handheld devices 2007-12-25
6526583 Interactive set-top box having a unified memory architecture David Auld, Hong-Jyeh Jason Huang, Gerard K. Yeh 2003-02-25
6466220 Graphics engine architecture Joseph Cesana, Peter Trajmar, Edward Wang, Hank Guo, Steve Chiou +1 more 2002-10-15
6434689 Data processing unit with interface for sharing registers by a processor and a coprocessor Rod G. Fleck, Roger D. Arnold, Danielle G. Lemay 2002-08-13
6411334 Aspect ratio correction using digital filtering Gerard K. Yeh, Anoush Khazeni, David Auld, Meng-Day Yu 2002-06-25
6292845 Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively Rod G. Fleck, Ole H. M.o slashed.ller, Roger D. Arnold, Balraj Singh 2001-09-18
6128641 Data processing unit with hardware assisted context switching capability Rod G. Fleck, Roger D. Arnold, Vojin G. Oklobdzija, Eric Chesters 2000-10-03