{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Tera Logic", "item": "https://www.patentleaderboard.com/company/tera-logic"}, {"@type": "ListItem", "position": 3, "name": "Peter Trajmar", "item": "https://www.patentleaderboard.com/inventor/fl:pe_ln:trajmar-1"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
PT

Peter Trajmar — 5 Patents

TLTera Logic: 4 patents #5 of 20Top 25%
ZOZoran: 1 patents #83 of 200Top 45%
San Jose, CA: #10,871 of 32,062 inventorsTop 35%
California: #107,996 of 386,348 inventorsTop 30%
Overall (All Time): #907,971 of 4,157,543Top 25%
5 Patents All Time
Peter Trajmar has been granted 5 US patents while listed as an inventor at Tera Logic. The first was granted in 2001 and the most recent in January 2012. Peter Trajmar ranks #907,971 of 4,157,543 US inventors in our database (top 21.8%). Patent records list Peter Trajmar in San Jose, CA, US.

Patents per Year

Patents granted per year, 2001 to 2012Bar chart with a peak of 2 patents in 2002.peak 22001: 1 patents20012002: 2 patents20022003: 1 patents20032012: 1 patents2012

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
8098737 Robust multi-tuner/multi-channel audio/video rendering on a single-chip high-definition digital multimedia receiver Nishit Kumar, Gerard K. Yeh 2012-01-17
6556193 De-interlacing video images using patch-based processing David Auld, Gerard K. Yeh 2003-04-29
6466220 Graphics engine architecture Joseph Cesana, Edward Wang, Hank Guo, Steve Chiou, Bruce Holmer +1 more 2002-10-15
6411333 Format conversion using patch-based filtering David Auld, Gerard K. Yeh, C. Dardy Chang, Kevin P. Acken 2002-06-25
6327000 Efficient image scaling for scan rate conversion David Auld, Gerard K. Yeh, C. Dardy Chang, Meng-Day Yu 2001-12-04