Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7774585 | Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation | Robert E. Ober, Daniel F. Martin, Erik K. Norden | 2010-08-10 |
| 7546442 | Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions | David Allen Fotland, Tibet Mimaroglu | 2009-06-09 |
| 7360203 | Program tracing in a multithreaded processor | Robert E. Ober, Daniel F. Martin, Erik K. Norden | 2008-04-15 |
| 7263599 | Thread ID in a multithreaded processor | Erik K. Norden, Robert E. Ober, Daniel F. Martin | 2007-08-28 |
| 7260707 | Variable length instruction pipeline | Erik K. Norden, Robert E. Ober, Neil Hastie | 2007-08-21 |
| 7159103 | Zero-overhead loop operation in microprocessor having instruction buffer | Sagheer Ahmad, Matthias Knoth | 2007-01-02 |
| 7062606 | Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events | Robert E. Ober, Daniel F. Martin, Erik K. Norden | 2006-06-13 |
| 7047396 | Fixed length memory to memory arithmetic and architecture for a communications embedded processor system | David Allen Fotland, Tibet Mimaroglu | 2006-05-16 |
| 6859873 | Variable length instruction pipeline | Erik K. Norden, Robert E. Ober, Neil Hastie | 2005-02-22 |
| 6434689 | Data processing unit with interface for sharing registers by a processor and a coprocessor | Rod G. Fleck, Bruce Holmer, Danielle G. Lemay | 2002-08-13 |
| 6378065 | Apparatus with context switching capability | Alfred Eder | 2002-04-23 |
| 6292845 | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively | Rod G. Fleck, Bruce Holmer, Ole H. M.o slashed.ller, Balraj Singh | 2001-09-18 |
| 6175913 | Data processing unit with debug capabilities using a memory protection unit | Eric Chesters, Rod G. Fleck | 2001-01-16 |
| 6128641 | Data processing unit with hardware assisted context switching capability | Rod G. Fleck, Bruce Holmer, Vojin G. Oklobdzija, Eric Chesters | 2000-10-03 |
| 6041387 | Apparatus for read/write-access to registers having register file architecture in a central processing unit | Rod G. Fleck | 2000-03-21 |
| 4583725 | Patient support frame for posterior lumbar laminectomy | — | 1986-04-22 |