Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417047 | Heterogeneous ML accelerator cluster with flexible system resource balance | Sheng Li, Sridhar Lakshmanamurthy, Norman Paul Jouppi, Martin G. Dixon, Daniel Stodolsky +3 more | 2025-09-16 |
| 12393443 | Systems and methods for task switching in neural network processor | Liran Fishel | 2025-08-19 |
| 12393824 | Methods and apparatus for a knowledge-based deep learning refactoring model with tightly integrated functional nonparametric memory | Gadi Singer, Nagib Hakim, Phillip Howard, Daniel Korat, Vasudev Lal +5 more | 2025-08-19 |
| 12282838 | Systems and methods for assigning tasks in a neural network processor | Liran Fishel | 2025-04-22 |
| 11989640 | Scalable neural network processing engine | Liran Fishel, Sung Hee Park, Jaewon Shin, Christopher L. Mills, Seungjin Lee +1 more | 2024-05-21 |
| 11740932 | Systems and methods for task switching in neural network processor | Liran Fishel | 2023-08-29 |
| 11537838 | Scalable neural network processing engine | Liran Fishel, Sung Hee Park, Jaewon Shin, Christopher L. Mills, Seungjin Lee +1 more | 2022-12-27 |
| 11487846 | Performing multiply and accumulate operations in neural network processor | Christopher L. Mills, Sung Hee Park | 2022-11-01 |
| 10970078 | Computation engine with upsize/interleave and downsize/deinterleave options | Eric Bainville, Tal Uliel, Jeffry E. Gonion, Ali Sazegari | 2021-04-06 |
| 10877754 | Matrix computation engine | Eric Bainville, Tal Uliel, Jeffry E. Gonion, Ali Sazegari | 2020-12-29 |
| 10776114 | Variable register and immediate field encoding in an instruction set architecture | — | 2020-09-15 |
| 10592239 | Matrix computation engine | Eric Bainville, Tal Uliel, Jeffry E. Gonion, Ali Sazegari | 2020-03-17 |
| 10346163 | Matrix computation engine | Eric Bainville, Tal Uliel, Jeffry E. Gonion, Ali Sazegari | 2019-07-09 |
| 9928065 | Variable register and immediate field encoding in an instruction set architecture | — | 2018-03-27 |
| 9274796 | Variable register and immediate field encoding in an instruction set architecture | — | 2016-03-01 |
| 8392644 | System and method for automatic hardware interrupt handling | David Yiu-Man Lau, James Hippisley Robinson | 2013-03-05 |
| 7774585 | Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation | Robert E. Ober, Roger D. Arnold, Daniel F. Martin | 2010-08-10 |
| 7360203 | Program tracing in a multithreaded processor | Robert E. Ober, Daniel F. Martin, Roger D. Arnold | 2008-04-15 |
| 7296134 | Fast unaligned memory access system and method | Klaus Oberlaender | 2007-11-13 |
| 7263599 | Thread ID in a multithreaded processor | Robert E. Ober, Roger D. Arnold, Daniel F. Martin | 2007-08-28 |
| 7260707 | Variable length instruction pipeline | Roger D. Arnold, Robert E. Ober, Neil Hastie | 2007-08-21 |
| 7222251 | Microprocessor idle mode management system | Sagheer Ahmad, Rob Ober | 2007-05-22 |
| 7062606 | Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events | Robert E. Ober, Roger D. Arnold, Daniel F. Martin | 2006-06-13 |
| 6859873 | Variable length instruction pipeline | Roger D. Arnold, Robert E. Ober, Neil Hastie | 2005-02-22 |