Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394560 | Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor | Vyacheslav V. Malyugin, Min Xu, Boris Weissman, Ganesh Venkitachalam | 2019-08-27 |
| 10108424 | Profiling code portions to generate translations | Nathan Tuck, Ross Segelken, David Dunn, Ben Hertzberg, Rupert Brauch +3 more | 2018-10-23 |
| 9891972 | Lazy runahead operation for a microprocessor | Magnus Ekman, Ross Segelken, Guillermo J. Rozas, James van Zoeren, Paul Serris +4 more | 2018-02-13 |
| 9823931 | Queued instruction re-dispatch after runahead | Guillermo J. Rozas, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan +6 more | 2017-11-21 |
| 9740553 | Managing potentially invalid results during runahead | Bruce Holmer, Guillermo J. Rozas, James van Zoeren, Paul Serris, Brad Hoyt +5 more | 2017-08-22 |
| 9652244 | Processing bypass directory tracking system and method | Guillermo J. Rozas | 2017-05-16 |
| 9645929 | Speculative permission acquisition for shared memory | James van Zoeren, Guillermo J. Rozas, Paul Serris | 2017-05-09 |
| 9632976 | Lazy runahead operation for a microprocessor | Guillermo J. Rozas, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan +4 more | 2017-04-25 |
| 9552208 | System, method, and computer program product for remapping registers based on a change in execution mode | Ben Hertzberg, Guillermo J. Rozas, Nickolas Andrew Fortino | 2017-01-24 |
| 9547602 | Translation lookaside buffer entry systems and methods | Guillermo J. Rozas | 2017-01-17 |
| 9436471 | Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor | Vyacheslav V. Malyugin, Min Xu, Boris Weissman, Ganesh Venkitachalam | 2016-09-06 |
| 9317284 | Vector hazard check instruction with reduced source operands | Jeffry E. Gonion | 2016-04-19 |
| 8924648 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2014-12-30 |
| 8607025 | Data structure for enforcing consistent per-physical page cacheability attributes | David Dunn | 2013-12-10 |
| 8566564 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2013-10-22 |
| 8473946 | Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor | Vyacheslav V. Malyugin, Min Xu, Boris Weissman, Ganesh Venkitachalam | 2013-06-25 |
| 8464033 | Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream | Guillermo J. Rozas | 2013-06-11 |
| 8370604 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2013-02-05 |
| 8239656 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, H. Peter Anvin, David Dunn | 2012-08-07 |
| 8209518 | Processing bypass directory tracking system and method | Guillermo J. Rozas | 2012-06-26 |
| 8127098 | Virtualization of real mode execution | Kevin J. McGrath, Hongwen Gao | 2012-02-28 |
| 8117421 | Data structure for enforcing consistent per-physical page cacheability attributes | David Dunn | 2012-02-14 |
| 8019983 | Setting a flag bit to defer event handling to a safe point in an instruction stream | Guillermo J. Rozas | 2011-09-13 |
| 7979669 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2011-07-12 |
| 7962909 | Limiting guest execution | — | 2011-06-14 |