Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7937566 | Processing bypass directory tracking system and method | Guillermo J. Rozas | 2011-05-03 |
| 7937536 | Handling direct memory accesses | Guillermo J. Rozas, David Dunn | 2011-05-03 |
| 7937700 | System, processor, and method for incremental state save/restore on world switch in a virtual machine environment | Michael Shawn Greske, Hongwen Gao | 2011-05-03 |
| 7917740 | Virtualization assist for legacy x86 floating point exception handling | Michael Shawn Greske | 2011-03-29 |
| 7913058 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, H. Peter Anvin, David Dunn | 2011-03-22 |
| 7873793 | Supporting speculative modification in a data cache | Guillermo J. Rozas, David Dunn, Paul Serris, Lacky V. Shah | 2011-01-18 |
| 7774583 | Processing bypass register file system and method | Parag Gupta, James van Zoeren | 2010-08-10 |
| 7725656 | Braided set associative caching techniques | Guillermo J. Rozas, Robert P. Masleid, John Banning, James Van Zoeren, Paul Serris | 2010-05-25 |
| 7707341 | Virtualizing an interrupt controller | William A. Hughes | 2010-04-27 |
| 7676629 | Data structure for enforcing consistent per-physical page cacheability attributes | David Dunn | 2010-03-09 |
| 7636815 | System and method for handling direct memory accesses | Guillermo J. Rozas, David Dunn | 2009-12-22 |
| 7620779 | System and method for handling direct memory accesses | Guillermo J. Rozas, David Dunn | 2009-11-17 |
| 7606979 | Method and system for conservatively managing store capacity available to a processor issuing stores | Guillermo J. Rozas, David Dunn, Paul Serris, Lacky V. Shah | 2009-10-20 |
| 7606997 | Method and system for using one or more address bits and an instruction to increase an instruction set | Guillermo J. Rozas, Eric Hao | 2009-10-20 |
| 7478226 | Processing bypass directory tracking system and method | Guillermo J. Rozas | 2009-01-13 |
| 7418584 | Executing system management mode code as virtual machine guest | Geoffrey S. Strongin, Kevin J. McGrath | 2008-08-26 |
| 7380098 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2008-05-27 |
| 7380096 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, H. Peter Anvin, David Dunn | 2008-05-27 |
| 7310723 | Methods and systems employing a flag for deferring exception handling to a commit or rollback point | Guillermo J. Rozas | 2007-12-18 |
| 7225299 | Supporting speculative modification in a data cache | Guillermo J. Rozas, David Dunn, Paul Serris, Lacky V. Shah | 2007-05-29 |
| 7209994 | Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests | Hongwen Gao | 2007-04-24 |
| 7149872 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, H. Peter Anvin, David Dunn | 2006-12-12 |
| 7149851 | Method and system for conservatively managing store capacity available to a processor issuing stores | Guillermo J. Rozas, David Dunn, Paul Serris, Lacky V. Shah | 2006-12-12 |
| 7089397 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Guillermo J. Rozas, John Banning | 2006-08-08 |
| 7062631 | Method and system for enforcing consistent per-physical page cacheability attributes | David Dunn | 2006-06-13 |