Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7971002 | Maintaining instruction coherency in a translation-based computer system architecture | Guillermo J. Rozas | 2011-06-28 |
| 7958296 | System management and advanced programmable interrupt controller | — | 2011-06-07 |
| 7937536 | Handling direct memory accesses | Alexander Klaiber, Guillermo J. Rozas | 2011-05-03 |
| 7925815 | Modifications to increase computer system security | — | 2011-04-12 |
| 7913058 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, Alexander Klaiber, H. Peter Anvin | 2011-03-22 |
| 7873793 | Supporting speculative modification in a data cache | Guillermo J. Rozas, Alexander Klaiber, Paul Serris, Lacky V. Shah | 2011-01-18 |
| 7840788 | Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register | Guillermo J. Rozas, Robert F. Cmelik | 2010-11-23 |
| 7810002 | Providing trusted access to a JTAG scan interface in a microprocessor | Keith Klayman | 2010-10-05 |
| 7779241 | History based pipelined branch prediction | John Banning | 2010-08-17 |
| 7676629 | Data structure for enforcing consistent per-physical page cacheability attributes | Alexander Klaiber | 2010-03-09 |
| 7636815 | System and method for handling direct memory accesses | Alexander Klaiber, Guillermo J. Rozas | 2009-12-22 |
| 7634635 | Systems and methods for reordering processor instructions | Brian Holscher, Guillermo J. Rozas, James van Zoeren | 2009-12-15 |
| 7634701 | Method and system for protecting processors from unauthorized debug access | Andrew Morgan | 2009-12-15 |
| 7620779 | System and method for handling direct memory accesses | Alexander Klaiber, Guillermo J. Rozas | 2009-11-17 |
| 7610426 | System management mode code modifications to increase computer system security | — | 2009-10-27 |
| 7606979 | Method and system for conservatively managing store capacity available to a processor issuing stores | Guillermo J. Rozas, Alexander Klaiber, Paul Serris, Lacky V. Shah | 2009-10-20 |
| 7600166 | Method and system for providing trusted access to a JTAG scan interface in a microprocessor | Keith Klayman | 2009-10-06 |
| 7451300 | Explicit control of speculation | H. Peter Anvin | 2008-11-11 |
| 7380096 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, Alexander Klaiber, H. Peter Anvin | 2008-05-27 |
| 7337307 | Exception handling with inserted status check command accommodating floating point instruction forward move across branch | Guillermo J. Rozas, Robert F. Cmelik | 2008-02-26 |
| 7334173 | Method and system for protecting processors from unauthorized debug access | Andrew Morgan | 2008-02-19 |
| 7225299 | Supporting speculative modification in a data cache | Guillermo J. Rozas, Alexander Klaiber, Paul Serris, Lacky V. Shah | 2007-05-29 |
| 7149851 | Method and system for conservatively managing store capacity available to a processor issuing stores | Guillermo J. Rozas, Alexander Klaiber, Paul Serris, Lacky V. Shah | 2006-12-12 |
| 7149872 | System and method for identifying TLB entries associated with a physical address of a specified range | Guillermo J. Rozas, Alexander Klaiber, H. Peter Anvin | 2006-12-12 |
| 7062631 | Method and system for enforcing consistent per-physical page cacheability attributes | Alexander Klaiber | 2006-06-13 |