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USPTO Patent Rankings Data through Dec 31, 2025
AS

Andrew Shaw — 7 Patents

TRTransmeta: 3 patents #29 of 86Top 35%
JPMorgan Chase: 1 patents #2,632 of 3,779Top 70%
Overall (All Time): #680,018 of 4,157,543Top 20%
7 Patents All Time
Andrew Shaw has been granted 7 US patents while listed as an inventor at Transmeta. The first was granted in 1999 and the most recent in July 2025. Andrew Shaw ranks #680,018 of 4,157,543 US inventors in our database (top 16.4%). Patent records list Andrew Shaw in Glasgow, MA, GB.

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12353635 Method and system for gesture recognition Vlad Zaharovs 2025-07-08
8438548 Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version John Banning, H. Peter Anvin, Robert Bedicheck, Guillermo J. Rozas, Linus Torvalds +1 more 2013-05-07
7904891 Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Linus Torvalds +1 more 2011-03-08
7404181 Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Linus Torvalds +1 more 2008-07-22 $9,792,000
7096460 Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Linus Torvalds +1 more 2006-08-22 $3,834,000
6594821 Translation consistency checking for modified target instructions by comparing to original copy John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Linus Torvalds +1 more 2003-07-15 $4,776,000
5991866 Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system Steven K. Heller 1999-11-23