GR

Guillermo J. Rozas

NV NVIDIA: 21 patents #277 of 7,811Top 4%
TR Transmeta: 21 patents #1 of 86Top 2%
IN Intel: 3 patents #10,349 of 30,777Top 35%
HP HP: 2 patents #2,312 of 7,018Top 35%
Meta: 1 patents #4,098 of 6,845Top 60%
Broadcom: 1 patents #5,847 of 9,346Top 65%
📍 Los Gatos, CA: #47 of 2,986 inventorsTop 2%
🗺 California: #2,521 of 386,348 inventorsTop 1%
Overall (All Time): #16,489 of 4,157,543Top 1%
94
Patents All Time

Issued Patents All Time

Showing 26–50 of 94 patents

Patent #TitleCo-InventorsDate
9081563 Method and apparatus for enhancing scheduling in an advanced microprocessor Godfrey P. D'Souza, Charles R. Price, Paul Serris 2015-07-14
8924648 Method and system for caching attribute data for matching attributes with physical addresses H. Peter Anvin, Alexander Klaiber, John Banning 2014-12-30
8898395 Memory management for cache consistency 2014-11-25
8751753 Coherence de-coupling buffer 2014-06-10
8677106 Unanimous branch instructions in a parallel thread processor John R. Nickolls, Richard Craig Johnson, Robert Steven Glanville 2014-03-18
8656214 Dual ported replicated data cache Alex Klaiber, Robert P. Masleid 2014-02-18
8650555 Method for increasing the speed of speculative execution Richard P. Johnson 2014-02-11
8615646 Unanimous branch instructions in a parallel thread processor John R. Nickolls, Richard Craig Johnson, Robert Steven Glanville 2013-12-24
8572355 Support for non-local returns in parallel thread SIMD engine Brett W. Coon 2013-10-29
8566564 Method and system for caching attribute data for matching attributes with physical addresses H. Peter Anvin, Alexander Klaiber, John Banning 2013-10-22
8522253 Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches Alex Klaiber 2013-08-27
8508262 Signal generator with output frequency greater than the oscillator frequency William N. Schnaitter 2013-08-13
8464033 Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream Alexander Klaiber 2013-06-11
8438548 Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version John Banning, H. Peter Anvin, Robert Bedicheck, Andrew Shaw, Linus Torvalds +1 more 2013-05-07
8413162 Multi-threading based on rollback Michael Neilly 2013-04-02
8370604 Method and system for caching attribute data for matching attributes with physical addresses H. Peter Anvin, Alexander Klaiber, John Banning 2013-02-05
8239656 System and method for identifying TLB entries associated with a physical address of a specified range Alexander Klaiber, H. Peter Anvin, David Dunn 2012-08-07
8209518 Processing bypass directory tracking system and method Alexander Klaiber 2012-06-26
8209517 Method and apparatus for enhancing scheduling in an advanced microprocessor Godfrey P. D'Souza, Charles R. Price, Paul Serris 2012-06-26
8035430 Signal generator with output frequency greater than the oscillator frequency William N. Schnaitter 2011-10-11
8019983 Setting a flag bit to defer event handling to a safe point in an instruction stream Alexander Klaiber 2011-09-13
7979669 Method and system for caching attribute data for matching attributes with physical addresses H. Peter Anvin, Alexander Klaiber, John Banning 2011-07-12
7971002 Maintaining instruction coherency in a translation-based computer system architecture David Dunn 2011-06-28
7937536 Handling direct memory accesses Alexander Klaiber, David Dunn 2011-05-03
7937566 Processing bypass directory tracking system and method Alexander Klaiber 2011-05-03