Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7334109 | Method and apparatus for improving segmented memory addressing | H. Peter Anvin, Alex Klaiber, Parag Gupta | 2008-02-19 |
| 7310723 | Methods and systems employing a flag for deferring exception handling to a commit or rollback point | Alexander Klaiber | 2007-12-18 |
| 7249246 | Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions | John Banning, H. Peter Anvin | 2007-07-24 |
| 7225299 | Supporting speculative modification in a data cache | Alexander Klaiber, David Dunn, Paul Serris, Lacky V. Shah | 2007-05-29 |
| 7149872 | System and method for identifying TLB entries associated with a physical address of a specified range | Alexander Klaiber, H. Peter Anvin, David Dunn | 2006-12-12 |
| 7149851 | Method and system for conservatively managing store capacity available to a processor issuing stores | Alexander Klaiber, David Dunn, Paul Serris, Lacky V. Shah | 2006-12-12 |
| 7096460 | Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation | John Banning, H. Peter Anvin, Robert Bedichek, Andrew Shaw, Linus Torvalds +1 more | 2006-08-22 |
| 7089404 | Method and apparatus for enhancing scheduling in an advanced microprocessor | Godfrey P. D'Souza, Charles R. Price, Paul Serris | 2006-08-08 |
| 7089397 | Method and system for caching attribute data for matching attributes with physical addresses | H. Peter Anvin, Alexander Klaiber, John Banning | 2006-08-08 |
| 6851040 | Method and apparatus for improving segmented memory addressing | H. Peter Anvin, Alex Klaiber, Parag Gupta | 2005-02-01 |
| 6826682 | Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state | David Dunn, Robert F. Cmelik | 2004-11-30 |
| 6748589 | Method for increasing the speed of speculative execution | Richard P. Johnson | 2004-06-08 |
| 6738893 | Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations | — | 2004-05-18 |
| 6725361 | Method and apparatus for emulating a floating point stack in a translation process | David Dunn, David Dobrikin, Alex Klaiber, Daniel H. Nelsen | 2004-04-20 |
| 6594821 | Translation consistency checking for modified target instructions by comparing to original copy | John Banning, H. Peter Anvin, Robert Bedichek, Andrew Shaw, Linus Torvalds +1 more | 2003-07-15 |
| 6470339 | Resource access control in a software system | Alan H. Karp, Rajiv Gupta, Arindam Banerji, Chia-Chiang Chao, Ernest Mak +2 more | 2002-10-22 |
| 6370639 | Processor architecture having two or more floating-point status fields | Jerome C. Huck, Peter Markstein, Glenn T. Colon-Bonet, Alan H. Karp, Roger Golliver +2 more | 2002-04-09 |
| 6205466 | Infrastructure for an open digital services marketplace | Alan H. Karp, Rajiv Gupta, Arindam Banerji, Ernest Mak, Sandeep Kumar +3 more | 2001-03-20 |
| 6151669 | Methods and apparatus for efficient control of floating-point status register | Jerome C. Huck, Peter Markstein, Glenn T. Colon-Bonet, Alan H. Karp, Roger Golliver +2 more | 2000-11-21 |