Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502559 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Tsung-Hsing Yu, Shih-Syuan Huang, Ken-Ichi Goto | 2016-11-22 |
| 9502409 | Multi-gate semiconductor devices | Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu +3 more | 2016-11-22 |
| 9455346 | Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage | Zhiqiang Wu, Tzer-Min Shen, Chun-Fu Cheng, Hong-Shen Chen | 2016-09-27 |
| 9425099 | Epitaxial channel with a counter-halo implant to improve analog gain | Tsung-Hsing Yu, Shih-Syuan Huang, Ken-Ichi Goto | 2016-08-23 |
| 9419136 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Tsung-Hsing Yu, Shih-Syuan Huang, Ken-Ichi Goto | 2016-08-16 |
| 9349655 | Method for mechanical stress enhancement in semiconductor devices | Carlos H. Diaz, Anson Wang, Kong-Beng Thei, Sheng-Chen Chung, Hao-Yi Tsai +3 more | 2016-05-24 |
| 9281372 | Metal gate structure and manufacturing method thereof | Shin-Jiun Kuang, Tsung-Hsing Yu, Chun-Yi Lee | 2016-03-08 |
| 9252236 | Counter pocket implant to improve analog gain | Shih-Syuan Huang, Tsung-Hsing Yu | 2016-02-02 |
| 8987824 | Multi-gate semiconductor devices | Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu +3 more | 2015-03-24 |
| 8981479 | Multi-gate semiconductor devices and methods of forming the same | Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu +2 more | 2015-03-17 |
| 8859380 | Integrated circuits and manufacturing methods thereof | Zhiqiang Wu, Tsung-Hsing Yu, Kuan-Lun Cheng, Chih-Pin Tsao, Wen-Yuan Chen +2 more | 2014-10-14 |
| 8623716 | Multi-gate semiconductor devices and methods of forming the same | Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu +2 more | 2014-01-07 |
| 8587075 | Tunnel field-effect transistor with metal source | Krishna Kumar Bhuwalka, Carlos H. Diaz | 2013-11-19 |
| 8354718 | Semiconductor device including an arrangement for suppressing short channel effects | Chih-Chiang Wang, Ying-Shiou Lin | 2013-01-15 |
| 7598130 | Method for reducing layout-dependent variations in semiconductor devices | Chung-Heng Yang, Sheng-Jier Yang | 2009-10-06 |
| 7545001 | Semiconductor device having high drive current and method of manufacture therefor | Shui-Ming Cheng, Ka-Hing Fung, Kuan-Lun Cheng | 2009-06-09 |
| 7429769 | Recessed channel field effect transistor (FET) device | Carlos H. Diaz, Syun-Ming Jang, Hun-Jan Tao, Fu-Liang Yang | 2008-09-30 |
| 7399679 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation | Da-Wen Lin, Cheng-Ku Chen, Po-Ying Yeh, Shi-Shung Peng, Chung-Cheng Wu | 2008-07-15 |
| 7371629 | N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications | Chu-Yun Fu, Chi-Hsun Hsieh, Syun-Ming Jang | 2008-05-13 |
| 7071515 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation | Da-Wen Lin, Cheng-Ku Chen, Po-Ying Yeh, Shi-Shung Peng, Chung-Cheng Wu | 2006-07-04 |
| 7012014 | Recessed gate structure with reduced current leakage and overlap capacitance | Da-Wen Lin, Ying-Keung Leung | 2006-03-14 |
| 6974730 | Method for fabricating a recessed channel field effect transistor (FET) device | Carlos H. Diaz, Syun-Ming Jang, Hun-Jan Tao, Fu-Liang Yang | 2005-12-13 |
| 6800516 | Electrostatic discharge device protection structure | Yi-Ling Chan, Fu-Liang Yang | 2004-10-05 |
| 6703187 | Method of forming a self-aligned twin well structure with a single mask | Fu-Liang Yang | 2004-03-09 |
| 6673683 | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions | Yi-Ling Chan, Da-Wen Lin, Wan-Yih Lien, Carlos H. Diaz | 2004-01-06 |