Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162928 | Method of designing a semiconductor device, system for implementing the method and standard cell | Nien-Yu Tsai, Chin-Chang Hsu, Hsien-Hsin Sean Lee | 2018-12-25 |
| 10121694 | Methods of manufacturing a semiconductor device | Yu-Jung Chang, Chin-Chang Hsu, Ying-Yu Shen, Nien-Yu Tsai | 2018-11-06 |
| 10013520 | Method of determining if layout design is N-colorable | Hung-Lung Lin, Chin-Chang Hsu, Chien Lin Ho | 2018-07-03 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2017-08-29 |
| 9514266 | Method and system of determining colorability of a layout | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Chun Huang | 2016-12-06 |
| 9471744 | Triple-pattern lithography layout decomposition | Hung-Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai, Chien Lin Ho | 2016-10-18 |
| 9465901 | Stretch dummy cell insertion in finFET process | Li Ke, Jia-Rong Hsu, Hung-Lung Lin | 2016-10-11 |
| 9449140 | Conflict detection for self-aligned multiple patterning compliance | Chin-Chang Hsu, HungLung Lin, Ying-Yu Shen, Ken-Hsien Hsieh | 2016-09-20 |
| 9360750 | Balancing mask loading | HungLung Lin, Chin-Chang Hsu | 2016-06-07 |
| 9318504 | Density gradient cell array | Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Chung-Min Fu | 2016-04-19 |
| 9223924 | Method and system for multi-patterning layout decomposition | Chin-Hsiung Hsu, Chin-Chang Hsu, Yuan-Te Hou, Godina Ho, Wen-Hao Chen | 2015-12-29 |
| 9213790 | Conflict detection for self-aligned multiple patterning compliance | Chin-Chang Hsu, HungLung Lin, Ying-Yu Shen, Ken-Hsien Hsieh | 2015-12-15 |
| 9147694 | Density gradient cell array | Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Chung-Min Fu | 2015-09-29 |
| 9147029 | Stretch dummy cell insertion in FinFET process | Li Ke, Jia-Rong Hsu, Hung-Lung Lin | 2015-09-29 |
| 9122836 | Recognition of template patterns with mask information | Chung-Min Fu, Yung-Fong Lu, Chin-Chang Hsu | 2015-09-01 |
| 9122838 | Triple-pattern lithography layout decomposition | Hung-Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai, Chien Lin Ho | 2015-09-01 |
| 9038010 | DRC format for stacked CMOS design | Yao-Jen Chuang, Nien-Yu Tsai | 2015-05-19 |
| 9026971 | Multi-patterning conflict free integrated circuit design | Chien Lin Ho, Chin-Chang Hsu, Hung-Lung Lin, Yi-Kan Cheng, Tsong-Hua Ou +5 more | 2015-05-05 |
| 8943445 | Method of merging color sets of layout | Pi-Tsung Chen, Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang +4 more | 2015-01-27 |
| 8943454 | In-phase grouping for voltage-dependent design rule | Chih Chi Hsiao, Jill Liu, Wei Hu, Jui-Feng Kuan, Yu-Ren Chen +2 more | 2015-01-27 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2014-12-09 |
| 8875065 | Triple-pattern lithography layout decomposition validation | Hung-Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai | 2014-10-28 |
| 8869090 | Stretch dummy cell insertion in FinFET process | Li Ke, Min-Yuan Tsai, Jia-Rong Hsu, Hung-Lung Lin | 2014-10-21 |
| 8782575 | Conflict detection for self-aligned multiple patterning compliance | Chin-Chang Hsu, HungLung Lin, Ying-Yu Shen, Ken-Hsien Hsieh | 2014-07-15 |
| 8775977 | Decomposition and marking of semiconductor device design layout in double patterning lithography | Chin-Chang Hsu, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu | 2014-07-08 |