Issued Patents All Time
Showing 201–221 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions | Chung Long Cheng, Harry-Hak-Lay Chuang | 2008-04-29 |
| 7332756 | Damascene gate structure with a resistive device | Chung Long Cheng, Harry Chuang | 2008-02-19 |
| 7298011 | Semiconductor device with recessed L-shaped spacer and method of fabricating the same | Chung Long Cheng, Harry Chuang | 2007-11-20 |
| 7157351 | Ozone vapor clean method | Chung Long Cheng, Jung-Hui Kao | 2007-01-02 |
| 7064056 | Barrier layer stack to prevent Ti diffusion | Chun-Lung Cheng, His-Chien Lin, Li-Don Chen, Tung-Lung Lai, Chi-Lung Lin | 2006-06-20 |
| 7030728 | Layout and method to improve mixed-mode resistor performance | Chih-Hsien Lin, Shyh-Chyi Wong | 2006-04-18 |
| 7026195 | Planarizing method for forming FIN-FET device | Chung Long Cheng | 2006-04-11 |
| 6881996 | Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer | Chun-Hon Chen, Ssu-Pin Ma, Ta-Hsun Yeh, Yen-Shih Ho, Kuo-Reay Peng +2 more | 2005-04-19 |
| 6812088 | Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer | Chun-Hon Chen, Ssu-Pin Ma, Ta-Hsun Yeh, Yen-Shih Ho, Kuo-Reay Peng +2 more | 2004-11-02 |
| 6732422 | Method of forming resistors | Chih-Hsien Lin, Shyh-Chyi Wong | 2004-05-11 |
| 6710413 | Salicide field effect transistors with improved borderless contact structures and a method of fabrication | Ming-Ta Lei, Shou-Gwo Wuu | 2004-03-23 |
| 6667217 | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process | Heng-Ming Hsu, Jau-Yuann Chung, Yen-Shih Ho, Chun-Hon Chen, Kuo-Reay Peng +2 more | 2003-12-23 |
| 6472721 | Dual damascene interconnect structures that include radio frequency capacitors and inductors | Ssu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu +2 more | 2002-10-29 |
| 6350662 | Method to reduce defects in shallow trench isolations by post liner anneal | Kuei-Ying Lee, Dun-Nian Yaung, Shou-Gwo Wuu | 2002-02-26 |
| 6335249 | Salicide field effect transistors with improved borderless contact structures and a method of fabrication | Ming-Ta Lei, Shou-Gwo Wuu | 2002-01-01 |
| 6329234 | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow | Ssu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu +2 more | 2001-12-11 |
| 6265271 | Integration of the borderless contact salicide process | Shou-Gwo Wuu | 2001-07-24 |
| 6214698 | Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer | Jhon Jhy Liaw, Jin-Yuan Lee, Kuei-Ying Lee, Chu-Yun Fu | 2001-04-10 |
| 6110793 | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits | Kuei-Ying Lee, Bou-Fun Chen | 2000-08-29 |
| 6080638 | Formation of thin spacer at corner of shallow trench isolation (STI) | Chung-Te Lin, Shwangming Jeng, Yuan-Horng Chiu | 2000-06-27 |
| 6046103 | Borderless contact process for a salicide devices | Ming Lei, Shou-Gwo Wuu | 2000-04-04 |