Issued Patents All Time
Showing 176–200 of 221 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7977202 | Reducing device performance drift caused by large spacings between active regions | Harry-Hak-Lay Chuang, Mong-Song Liang | 2011-07-12 |
| 7977181 | Method for gate height control in a gate last process | Su-Chen Lai, Harry-Hak-Lay Chuang | 2011-07-12 |
| 7955964 | Dishing-free gap-filling with multiple CMPs | Ming-Yuan Wu, Chiun-Han Yeh, Harry-Hak-Lay Chuang, Mong-Song Liang | 2011-06-07 |
| 7939384 | Eliminating poly uni-direction line-end shortening using second cut | Harry-Hak-Lay Chuang | 2011-05-10 |
| 7939392 | Method for gate height control in a gate last process | Sheng-Chen Chung, Harry-Hak-Lay Chuang | 2011-05-10 |
| 7927943 | Method for tuning a work function of high-k metal gate devices | Chiung-Han Yeh, Sheng-Chen Chung, Harry-Hak-Lay Chuang | 2011-04-19 |
| 7923321 | Method for gap filling in a gate last process | Su-Chen Lai, Harry-Hak-Lay Chuang, Gary Shen | 2011-04-12 |
| 7919792 | Standard cell architecture and methods with variable design rules | Oscar M. K. Law, Manoj Joshi, Harry-Hak-Lay Chuang | 2011-04-05 |
| 7898037 | Contact scheme for MOSFETs | Harry-Hak-Lay Chuang, Mong-Song Liang, Jung-Hui Kao, Sheng-Chen Chung, Chung Long Cheng +1 more | 2011-03-01 |
| 7868361 | Semiconductor device with both I/O and core components and method of fabricating same | Chung Long Cheng, Sheng-Chen Chung, Harry-Hak-Lay Chuang, Mong-Song Liang | 2011-01-11 |
| 7868386 | Method and apparatus for semiconductor device with improved source/drain junctions | Chung Long Cheng, Harry-Hak-Lay Chuang | 2011-01-11 |
| 7833848 | Method for removing hard masks on gates in semiconductor manufacturing process | Hung-Chih Tsai, Chih-Chieh Chen, Sheng-Chen Chung, Harry Chuang | 2010-11-16 |
| 7812379 | SOI devices | Chung Long Cheng, Sheng-Chen Chung, Tzung-Chi Lee, Harry Chuang | 2010-10-12 |
| 7803674 | Methods for fabricating SOI devices | Chung Long Cheng, Sheng-Chen Chung, Tzung-Chi Lee, Harry Chuang | 2010-09-28 |
| 7768069 | FIN-FET device structure | Chung Long Cheng | 2010-08-03 |
| 7750416 | Modifying work function in PMOS devices by counter-doping | Chun-Yi Lee, Harry-Hak-Lay Chuang, Ping-Wei Wang | 2010-07-06 |
| 7701034 | Dummy patterns in integrated circuit fabrication | Harry-Hak-Lay Chuang, Cheng-Cheng Kuo | 2010-04-20 |
| 7678636 | Selective formation of stress memorization layer | Harry-Hak-Lay Chuang, Mong-Song Liang, Jung-Hui Kao, Chung Long Cheng, Sheng-Chen Chung +1 more | 2010-03-16 |
| 7632729 | Method for semiconductor device performance enhancement | Harry Chuang, Chung Long Cheng, Sheng-Chen Chung, Wen-Huei Guo, Jung-Hui Kao +2 more | 2009-12-15 |
| 7612364 | MOS devices with source/drain regions having stressed regions and non-stressed regions | Harry-Hak-Lay Chuang, Yuan-Chen Sun | 2009-11-03 |
| 7550795 | SOI devices and methods for fabricating the same | Chung Long Cheng, Sheng-Chen Chung, Tzung-Chi Lee, Harry Chuang | 2009-06-23 |
| 7525177 | Controllable varactor within dummy substrate pattern | Chung Long Cheng, Sheng Lin | 2009-04-28 |
| 7470992 | Barrier layer stack to prevent Ti diffusion | Chun-Lung Cheng, Hsi-Chien Lin, Li-Don Chen, Tung-Lung Lai, Chi-Lung Lin | 2008-12-30 |
| 7432179 | Controlling gate formation by removing dummy gate structures | Harry-Hak-Lay Chuang | 2008-10-07 |
| 7404167 | Method for improving design window | Harry-Hak-Lay Chuang, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen | 2008-07-22 |