Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9748212 | Shadow pad for post-passivation interconnect structures | Shih-Wei Liang, Bor-Rung Su, Chang-Pin Huang, Chien-Chia Chiu, Chun-Hung Lin +1 more | 2017-08-29 |
| 9679883 | Hollow metal pillar packaging scheme | Chang-Pin Huang, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai | 2017-06-13 |
| 9640498 | Integrated fan-out (InFO) package structures and methods of forming same | Chang-Pin Huang, Chen-Hua Yu, Ching-Jung Yang, Chung-Shi Liu, Hung-Yi Kuo +3 more | 2017-05-02 |
| 9627332 | Integrated circuit structure and seal ring structure | Shih-Wei Liang, Ching-Jung Yang, Chang-Pin Huang, Yu-Chia Lai | 2017-04-18 |
| 9559044 | Package with solder regions aligned to recesses | Ching-Jung Yang, Hsien-Wei Chen, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao | 2017-01-31 |
| 9484318 | Semiconductor device and manufacturing method thereof | Tung-Liang Shao, Yu-Chia Lai, Chang-Pin Huang, Ching-Jung Yang | 2016-11-01 |
| 9461106 | MIM capacitor and method forming the same | Ching-Jung Yang, Chang-Pin Huang, Hao-Yi Tsai, Mirng-Ji Lii, Shih-Wei Liang +1 more | 2016-10-04 |
| 9343417 | Hollow metal pillar packaging scheme | Chang-Pin Huang, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai | 2016-05-17 |
| 9318456 | Self-alignment structure for wafer level chip scale package | Yu-Chia Lai, Tung-Liang Shao, Hsien-Wei Chen, Chang-Pin Huang, Ching-Jung Yang | 2016-04-19 |
| 9048149 | Self-alignment structure for wafer level chip scale package | Yu-Chia Lai, Tung-Liang Shao, Hsien-Wei Chen, Chang-Pin Huang, Ching-Jung Yang | 2015-06-02 |