Issued Patents All Time
Showing 26–50 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11276819 | Metal landing on top electrode of RRAM | Wen-Ting Chu | 2022-03-15 |
| 11249131 | Test apparatus and testing method using the same | Harry-Hak-Lay Chuang, Tien-Wei Chiang, Chia Yu Wang, Meng-Chun Shih, Ching-Huang Wang +2 more | 2022-02-15 |
| 11239279 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Hsia-Wei Chen, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2022-02-01 |
| 11201281 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2021-12-14 |
| 11201190 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao | 2021-12-14 |
| 11094744 | Interconnect landing method for RRAM technology | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2021-08-17 |
| 10903274 | Interconnect landing method for RRAM technology | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2021-01-26 |
| 10877089 | Semiconductor wafer testing system and related method for improving external magnetic field wafer testing | Harry-Hak-Lay Chuang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang | 2020-12-29 |
| 10868250 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You +2 more | 2020-12-15 |
| 10862029 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2020-12-08 |
| 10796759 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu +4 more | 2020-10-06 |
| 10763426 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2020-09-01 |
| 10749108 | Logic compatible RRAM structure and process | Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2020-08-18 |
| 10727275 | Memory layout for reduced line loading | Wen-Ting Chu | 2020-07-28 |
| 10700275 | RRAM cell structure with laterally offset BEVA/TEVA | Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2020-06-30 |
| 10680038 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao | 2020-06-09 |
| 10566519 | Method for forming a flat bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao +3 more | 2020-02-18 |
| 10566387 | Interconnect landing method for RRAM technology | Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu +1 more | 2020-02-18 |
| 10510953 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-12-17 |
| 10504963 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao | 2019-12-10 |
| 10475852 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Hsia-Wei Chen, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2019-11-12 |
| 10475999 | Metal landing on top electrode of RRAM | Wen-Ting Chu | 2019-11-12 |
| 10388868 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You +2 more | 2019-08-20 |
| 10311952 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu +4 more | 2019-06-04 |
| 10276790 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-04-30 |