Issued Patents All Time
Showing 76–100 of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812536 | Reverse tone self-aligned contact | Ching-Feng Fu, Yu-Chan Yen | 2017-11-07 |
| 9761451 | Cut last self-aligned litho-etch patterning | Kuan-Wei Huang, Ming-Chung Liang | 2017-09-12 |
| 9741621 | Nano wire structure and method for fabricating the same | Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chun-Hung Lee, Huan-Just Lin | 2017-08-22 |
| 9711372 | Double patterning method | Jyu-Horng Shieh | 2017-07-18 |
| 9698016 | Cut first self-aligned litho-etch patterning | Kuan-Wei Huang, Ming-Chung Liang | 2017-07-04 |
| 9633907 | Self-aligned nanowire formation using double patterning | Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chun-Hung Lee, Huan-Just Lin | 2017-04-25 |
| 9613903 | Fine line space resolution lithography structure for integrated circuit features using double patterning technology | Jyu-Horng Shieh | 2017-04-04 |
| 9601344 | Method of forming pattern for semiconductor device | Chih-Yuan Ting, Jyu-Horng Shieh, Ming-Hsing Tsai, Syun-Ming Jang | 2017-03-21 |
| 9570358 | Nano wire structure and method for fabricating the same | Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chun-Hung Lee, Huan-Just Lin | 2017-02-14 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh +1 more | 2017-02-07 |
| 9559386 | Voltage-enhanced energy storage devices | David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott | 2017-01-31 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Jyu-Horng Shieh +6 more | 2016-11-22 |
| 9496180 | Method of semiconductor integrated circuit fabrication | Kuen-Ming Liou | 2016-11-15 |
| 9437712 | High performance self aligned contacts and method of forming same | Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Tze-Liang Lee | 2016-09-06 |
| 9425049 | Cut first self-aligned litho-etch patterning | Kuan-Wei Huang, Ming-Chung Liang | 2016-08-23 |
| 9412614 | Nano wire structure and method for fabricating the same | Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chun-Hung Lee, Huan-Just Lin | 2016-08-09 |
| 9412656 | Reverse tone self-aligned contact | Ching-Feng Fu, Yu-Chan Yen | 2016-08-09 |
| 9406511 | Self-aligned double patterning | Kuan-Wei Huang, Ming-Chung Liang | 2016-08-02 |
| 9368349 | Cut last self-aligned litho-etch patterning | Kuan-Wei Huang, Ming-Chung Liang | 2016-06-14 |
| 9240346 | Double patterning method | Jyu-Horng Shieh | 2016-01-19 |
| 9204538 | Method of fine line space resolution lithography for integrated circuit features using double patterning technology | Jyu-Horng Shieh | 2015-12-01 |
| 9153478 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai +6 more | 2015-10-06 |
| 9117927 | Method of semiconductor integrated circuit fabrication | Kuen-Ming Liou | 2015-08-25 |
| 9040433 | Photo resist trimmed line end space | Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh +1 more | 2015-05-26 |
| 8987142 | Multi-patterning method and device formed by the method | Jyu-Horng Shieh | 2015-03-24 |