Issued Patents All Time
Showing 51–75 of 264 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840126 | FinFET structure with different fin heights and method for forming the same | Yu-Lien Huang, Chi Kang Liu | 2020-11-17 |
| 10825907 | Self-aligned contact and manufacturing method thereof | Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Yee-Chia Yeo | 2020-11-03 |
| 10763368 | Stacked gate-all-around FinFET and method forming the same | Kuo-Cheng Chiang, Ying-Keung Leung | 2020-09-01 |
| 10741646 | Field-effect transistors having contacts to 2D material active region | Ling-Yen Yeh, Yee-Chia Yeo | 2020-08-11 |
| 10727298 | Strained nanowire CMOS device and method of forming | Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo | 2020-07-28 |
| 10727135 | FinFET with sloped surface at interface between isolation structures and manufacturing method thereof | Chih-Sheng Li, Hsin-Chieh Huang | 2020-07-28 |
| 10700176 | Vertical gate all around (VGAA) devices and methods of manufacturing the same | Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Wai-Yi Lien +1 more | 2020-06-30 |
| 10679990 | Multi-fin device and method of making same | Chao-Hsiung Wang | 2020-06-09 |
| 10679900 | Fin spacer protected source and drain regions in FinFETs | Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang | 2020-06-09 |
| 10665718 | Wrap Around Silicide for FinFETs | Kuo-Cheng Chiang, Ying-Keung Leung | 2020-05-26 |
| 10658247 | FinFET devices and methods of forming | Kuo-Cheng Chiang | 2020-05-19 |
| 10636651 | Semiconductor device and method | Sheng-Ting Fan, Pin-Shiang Chen, Chee-Wee Liu | 2020-04-28 |
| 10622480 | Forming gate stacks of FinFETs through oxidation | Kuo-Cheng Chiang, Jiun-Jia Huang, Chao-Hsiung Wang | 2020-04-14 |
| 10535732 | Strained nanowire CMOS device and method of forming | Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo | 2020-01-14 |
| 10522640 | Metal gate scheme for device and methods of forming | Shiu-Ko JangJian, Chih-Nan Wu, Chun Che Lin | 2019-12-31 |
| 10504787 | FinFET with sloped surface at interface between isolation structures | Chih-Sheng Li, Hsin-Chieh Huang | 2019-12-10 |
| 10504907 | Antifuse array and method of forming antifuse using anodic oxidation | Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang | 2019-12-10 |
| 10505001 | Semiconductor device and method of forming the same | Chia-Ming Chang, Cheng-Chien Li, Hsin-Chieh Huang | 2019-12-10 |
| 10505052 | Semiconductor device with transition metal dichalocogenide hetero-structure | Shih-Yen Lin, Chong-Rong Wu, Xiang-Rui Chang | 2019-12-10 |
| 10505022 | Devices including gate spacer with gap or void and methods of forming the same | Kuo-Cheng Chiang, Ching-Wei Tsai, Ying-Keung Leung | 2019-12-10 |
| 10504770 | FinFET structure with different fin heights and method for forming the same | Yu-Lien Huang, Chi Kang Liu | 2019-12-10 |
| 10490654 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu | 2019-11-26 |
| 10483112 | Metal gate stack having TaAlCN layer | Shiu-Ko JangJian, Ting-Chun Wang, Chi-Cherng Jeng | 2019-11-19 |
| 10483208 | Interconnection structure, fabricating method thereof, and semiconductor device using the same | Yu-Hung Lin, Horng-Huei Tseng | 2019-11-19 |
| 10483367 | Vertical gate all around (VGAA) devices and methods of manufacturing the same | Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Wai-Yi Lien +1 more | 2019-11-19 |