Issued Patents All Time
Showing 76–100 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6207492 | Common gate and salicide word line process for low cost embedded DRAM devices | Kuo-Chyuan Tzeng, Tse-Liang Ying, Kevin Chiang | 2001-03-27 |
| 6201273 | Structure for a double wall tub shaped capacitor | Mong-Song Liang | 2001-03-13 |
| 6177340 | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure | Chue-San Yoo, Wen-Chuan Chiang | 2001-01-23 |
| 6037222 | Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology | Kuo-Ching Huang, Tse-Liang Ying, Jenn Ming Huang | 2000-03-14 |
| 6025279 | Method of reducing nitride and oxide peeling after planarization using an anneal | Min-Hsiung Chiang, Jenn Ming Huang | 2000-02-15 |
| 6017791 | Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer | Chue-San Yoo, Kuo-Hsien Cheng | 2000-01-25 |
| 6015730 | Integration of SAC and salicide processes by combining hard mask and poly definition | Jenn Ming Huang, Chue-San Yoo | 2000-01-18 |
| 6004857 | Method to increase DRAM capacitor via rough surface storage node plate | Yung Kuan Hsiao | 1999-12-21 |
| 6001731 | Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process | Chung-Hui Su, Mong-Song Liang, Shou-Gwo Wuu | 1999-12-14 |
| 5885865 | Method for making low-topography buried capacitor by a two stage etching process and device made | Mong-Song Liang, Julie Huang, Tse-Liang Ying | 1999-03-23 |
| 5867087 | Three dimensional polysilicon resistor for integrated circuits | Shou-Gwo Wuu, Mong-Song Liang, Chung-Hui Su | 1999-02-02 |
| 5858838 | Method for increasing DRAM capacitance via use of a roughened surface bottom capacitor plate | Chia-Shiung Tsai | 1999-01-12 |
| 5856220 | Method for fabricating a double wall tub shaped capacitor | Mong-Song Liang | 1999-01-05 |
| 5796135 | Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip | Mong-Song Liang, Shou-Gwo Wuu, Chung-Hui Su | 1998-08-18 |
| 5759892 | Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell | Mong-Song Liang | 1998-06-02 |
| 5759888 | Method for fabricating a DRAM cell with a Y shaped storage capacitor | Mong-Song Liang | 1998-06-02 |
| 5716881 | Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip | Mong-Song Liang, Shou-Gwo Wuu, Chung-Hui Su | 1998-02-10 |
| 5702989 | Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column | Mong-Song Liang | 1997-12-30 |
| 5677557 | Method for forming buried plug contacts on semiconductor integrated circuits | Shou-Gwo Wuu, Mong-Song Liang, Chung-Hui Su | 1997-10-14 |
| 5668380 | Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance | Shou-Gwo Wuu, Mong-Song Liang, Chung-Hui Su | 1997-09-16 |
| 5668038 | One step smooth cylinder surface formation process in stacked cylindrical DRAM products | Yuan-Chang Huang, Mong-Song Liang | 1997-09-16 |
| 5668035 | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology | Chung Hsin Fang, Julie Huang, Mong-Song Liang | 1997-09-16 |
| 5652174 | Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors | Shou-Gwo Wuu, Mong-Song Liang, Chung-Hui Su | 1997-07-29 |
| 5646061 | Two-layer polysilicon process for forming a stacked DRAM capacitor with improved doping uniformity and a controllable shallow junction contact | Mong-Song Liang | 1997-07-08 |
| 5607874 | Method for fabricating a DRAM cell with a T shaped storage capacitor | Mong-Song Liang | 1997-03-04 |