Issued Patents All Time
Showing 51–75 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8993405 | Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers | Kuo-Chyuan Tzeng, Luan C. Tran, Kuo-Chi Tu, Hsiang-Fan Lee | 2015-03-31 |
| 8994146 | Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers | Kuo-Chyuan Tzeng, Luan C. Tran, Kuo-Chi Tu, Hsiang-Fan Lee | 2015-03-31 |
| 8748284 | Method of manufacturing decoupling MIM capacitor designs for interposers | Kuo-Chyuan Tzeng, Kuo-Chi Tu, Hsiang-Fan Lee | 2014-06-10 |
| 8716100 | Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers | Kuo-Chyuan Tzeng, Luan C. Tran, Kuo-Chi Tu, Hsiang-Fan Lee | 2014-05-06 |
| 8659121 | Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof | Kuo-Chi Tu, Kuo-Chyuan Tzeng, Wen-Chuan Chiang | 2014-02-25 |
| 8617949 | Capacitor and method for making same | Kuo-Chi Tu, Wen-Chuan Chiang | 2013-12-31 |
| 8148223 | 1T MIM memory for embedded ram application in soc | Yi-Ching Lin, Chun-Yao Chen, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang +2 more | 2012-04-03 |
| 7282757 | MIM capacitor structure and method of manufacture | Kuo-Chi Tu, Chun-Yao Chen, Shou-Gwo Wuu | 2007-10-16 |
| 7208369 | Dual poly layer and method of manufacture | Chih-Yang Pai, Min-Hsiung Chiang, Shou-Gwo Wuu | 2007-04-24 |
| 6670664 | Single transistor random access memory (1T-RAM) cell with dual threshold voltages | Kuo-Chyuan Tzeng, Dennis Sinitsky, Wen-Chaun Chiang | 2003-12-30 |
| 6661049 | Microelectronic capacitor structure embedded within microelectronic isolation region | Kuo-Chyuan Tzeng, Chung-Wei Chang | 2003-12-09 |
| 6661050 | Memory cell structure with trench capacitor and method for fabrication thereof | Kuo-Chyuan Tzeng, Chung-Wei Chang | 2003-12-09 |
| 6638813 | Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell | Kuo-Chyuan Tzeng, Chung-Wei Chang, Wen-Chuan Chiang, Wen-Cheng Chen, Kuo-Ching Huang | 2003-10-28 |
| 6620679 | Method to integrate high performance 1T ram in a CMOS process using asymmetric structure | Kuo-Chyuan Tzeng, Dennis Sinitsky | 2003-09-16 |
| 6613690 | Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers | Chung-Wei Chang, Kuo-Chyuan Tzeng, Min-Hsiang Chiang, Chi-Hsing Lo | 2003-09-02 |
| 6538287 | Method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits | Dennis Sinitsky | 2003-03-25 |
| 6420226 | Method of defining a buried stack capacitor structure for a one transistor RAM cell | Wen-Cheng Chen, Kuo-Ching Huang, Wen-Chuan Chiang | 2002-07-16 |
| 6376294 | Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process | Kuo-Chyuan Tzeng, Wen-Chuan Chiang, Wen-Cheng Chen | 2002-04-23 |
| 6362041 | Method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits | Dennis Sinitsky | 2002-03-26 |
| 6338998 | Embedded DRAM fabrication method providing enhanced embedded DRAM performance | Chen-Yong Lin, Kevin Chiang | 2002-01-15 |
| 6271125 | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure | Chue-San Yoo, Wen-Chuan Chiang | 2001-08-07 |
| 6265301 | Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures | Jin-Yuan Lee | 2001-07-24 |
| 6242300 | Mixed mode process for embedded dram devices | — | 2001-06-05 |
| 6222214 | Plug structure and process for forming stacked contacts and metal contacts on static random access memory thin film transistors | Shou-Gwo Wuu, Mong-Song Liang, Chung-Hui Su | 2001-04-24 |
| 6218286 | Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process | Chung-Hui Su, Mong-Song Liang, Shou-Gwo Wuu | 2001-04-17 |