Issued Patents All Time
Showing 51–75 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6061711 | Efficient context saving and restoring in a multi-tasking computing system environment | Seungyoon Peter Song, Moataz A. Mohamed, Heonchul Park, Jerry R. Van Aken, Alessandro Forin +1 more | 2000-05-09 |
| 6058465 | Single-instruction-multiple-data processing in a multimedia signal processor | — | 2000-05-02 |
| 6044449 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Derek J. Lentz, Sho Long Chen | 2000-03-28 |
| 6038654 | High performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 6038653 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 6003129 | System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture | Seungyeon Peter Song, Moataz A. Mohamed, Heon-Chul Park | 1999-12-14 |
| 5996058 | System and method for handling software interrupts with argument passing | Seungyeon Peter Song, Moataz A. Mohamed, Heon-Chul Park | 1999-11-30 |
| 5987593 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl D. Senter, Johannes Wang, Brett W. Coon, Yoshiyuki Miyayama | 1999-11-16 |
| 5983334 | Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 1999-11-09 |
| 5978838 | Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor | Moataz A. Mohamed, Heonchul Park | 1999-11-02 |
| 5974526 | Superscalar RISC instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 1999-10-26 |
| 5974480 | DMA controller which receives size data for each DMA channel | Amjad Qureshi, Kab Ju Moon, Hoyoung Kim | 1999-10-26 |
| 5961628 | Load and store unit for a vector processor | Heonchul Park, Seong Rai Cho | 1999-10-05 |
| 5961629 | High performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1999-10-05 |
| 5941979 | Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 1999-08-24 |
| 5943250 | Parallel multiplier that supports multiple numbers with different bit lengths | Chang-Soo Kim, Roney S. Wong | 1999-08-24 |
| 5943251 | Adder which handles multiple data with different data types | Shao-Kun Jiang | 1999-08-24 |
| 5923862 | Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions | Heonchul Park | 1999-07-13 |
| 5889986 | Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer | Heonchul Park | 1999-03-30 |
| 5860158 | Cache control unit with a cache request transaction-oriented protocol | Yet-Ping Pai | 1999-01-12 |
| 5845112 | Method for performing dead-zone quantization in a single processor instruction | Heonchul Park, Cliff Reader, Yoon-tae Lee | 1998-12-01 |
| 5838984 | Single-instruction-multiple-data processing using multiple banks of vector registers | Seungyoon Peter Song, Moataz A. Mohamed, Heonchul Park, Roney S. Wong | 1998-11-17 |
| 5838986 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 1998-11-17 |
| 5831871 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Kevin R. Iadonato | 1998-11-03 |
| 5832292 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1998-11-03 |