Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5778434 | System and method for processing multiple requests and out of order returns | Yasuaki Hagiwara | 1998-07-07 |
| 5754800 | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 1998-05-19 |
| 5737624 | Superscalar risc instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 1998-04-07 |
| 5734584 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Kevin R. Iadonato | 1998-03-31 |
| 5689720 | High-performance superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1997-11-18 |
| 5682546 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 1997-10-28 |
| 5619666 | System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 1997-04-08 |
| 5604865 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 1997-02-18 |
| 5581742 | Apparatus and method for emulating a microelectronic device by interconnecting and running test vectors on physically implemented functional modules | Chong Ming Lin, Wai-Yan Ho | 1996-12-03 |
| 5581562 | Integrated circuit device implemented using a plurality of partially defective integrated circuit chips | Chong Ming Lin, Wai-Yan Ho | 1996-12-03 |
| 5566385 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Kevin R. Iadonato | 1996-10-15 |
| 5564117 | Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units | Derek J. Lentz, Johannes Wang, Trevor Deosaran, Linley M. Young, Kian-Chin Yap +2 more | 1996-10-08 |
| 5560035 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 1996-09-24 |
| 5559951 | Page printer controller including a single chip superscalar microprocessor with graphics functional units | Derek J. Lentz, Johannes Wang, Trevor Deosaran, Linley M. Young, Kian-Chin Yap +2 more | 1996-09-24 |
| 5560032 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-09-24 |
| 5546552 | Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 1996-08-13 |
| 5539911 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-07-23 |
| 5497499 | Superscalar risc instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 1996-03-05 |
| 5493687 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 1996-02-20 |
| 5481685 | RISC microprocessor architecture implementing fast trap and exception state | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1996-01-02 |
| 5448705 | RISC microprocessor architecture implementing fast trap and exception state | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1995-09-05 |
| 5440752 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 1995-08-08 |
| 5438668 | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 1995-08-01 |
| 5394515 | Page printer controller including a single chip superscalar microprocessor with graphics functional units | Derek J. Lentz, Johannes Wang, Trevor Deosaran, Linley M. Young, Kian-Chin Yap +2 more | 1995-02-28 |
| 5371684 | Semiconductor floor plan for a register renaming circuit | Kevin R. Iadonato | 1994-12-06 |