Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8074052 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2011-12-06 |
| 7979678 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2011-07-12 |
| 7802074 | Superscalar RISC instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 2010-09-21 |
| 7558945 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2009-07-07 |
| 7555738 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Le Trong Nguyen | 2009-06-30 |
| 7430651 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2008-09-30 |
| 7174525 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Le Trong Nguyen | 2007-02-06 |
| 7162616 | Floating point unit pipeline synchronized with processor pipeline | Prasenjit Biswas, Gautam Dewan, Norio Nakagawa, Kunio Uchiyama | 2007-01-09 |
| 7051187 | Superscalar RISC instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 2006-05-23 |
| 7043624 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2006-05-09 |
| 6970995 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2005-11-29 |
| 6922772 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2005-07-26 |
| 6782521 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Le Trong Nguyen | 2004-08-24 |
| 6772327 | Floating point unit pipeline synchronized with processor pipeline | Prasenjit Biswas, Gautam Dewan, Norio Nakagawa, Kunio Uchiyama | 2004-08-03 |
| 6757808 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2004-06-29 |
| 6418528 | Floating point unit pipeline synchronized with processor pipeline | Prasenjit Biswas, Gautam Dewan, Norio Nakagawa, Kunio Uchiyama | 2002-07-09 |
| 6408375 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2002-06-18 |
| 6401232 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Le Trong Nguyen | 2002-06-04 |
| 6360309 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2002-03-19 |
| 6289433 | Superscalar RISC instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 2001-09-11 |
| 6272617 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2001-08-07 |
| 6138231 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 2000-10-24 |
| 6092176 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 2000-07-18 |
| 6083274 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Le Trong Nguyen | 2000-07-04 |
| 5974526 | Superscalar RISC instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 1999-10-26 |