Issued Patents All Time
Showing 1–25 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11063701 | Safety integrity level of service (SILoS) system | Terry L. Fruehling | 2021-07-13 |
| 8019975 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl Senter Brashears, Johannes Wang, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg +4 more | 2011-09-13 |
| 7941636 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 2011-05-10 |
| 7941635 | High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2011-05-10 |
| 7802074 | Superscalar RISC instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 2010-09-21 |
| 7739482 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2010-06-15 |
| 7721070 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2010-05-18 |
| 7685402 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 2010-03-23 |
| 7664935 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 2010-02-16 |
| 7657712 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 2010-02-02 |
| 7555631 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Derek J. Lentz, Sho Long Chen | 2009-06-30 |
| 7555738 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Kevin R. Iadonato | 2009-06-30 |
| 7555632 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2009-06-30 |
| 7487333 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2009-02-03 |
| 7343473 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 2008-03-11 |
| 7174525 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Kevin R. Iadonato | 2007-02-06 |
| 7162610 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2007-01-09 |
| 7051187 | Superscalar RISC instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 2006-05-23 |
| 7028161 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2006-04-11 |
| 6986024 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2006-01-10 |
| 6965987 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl Senter Brashears, Johannes Wang, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg +4 more | 2005-11-15 |
| 6959375 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-10-25 |
| 6954844 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 2005-10-11 |
| 6954847 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 2005-10-11 |
| 6948052 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-09-20 |