Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020349 | Methods and apparatus for efficient blending in a graphics pipeline | David C. Tannenbaum | 2024-06-25 |
| 11227430 | Optimized pixel shader attribute management | Chris Goodman | 2022-01-18 |
| 11127109 | Methods and apparatus for avoiding lockup in a graphics pipeline | Chiachi Chao | 2021-09-21 |
| 11080924 | Optimized computation of perspective interpolants | Yevgeniy Urdenko | 2021-08-03 |
| 11010954 | Efficient redundant coverage discard mechanism to reduce pixel shader work in a tile-based graphics rendering pipeline | Nilanjan Goswami, Adithya H. Krishnamurthy, David C. Tannenbaum | 2021-05-18 |
| 10635439 | Efficient interface and transport mechanism for binding bindless shader programs to run-time specified graphics pipeline configurations and objects | Mitchell Alsup, David C. Tannenbaum, Srinivasan S. Iyer, Christopher James Goodman | 2020-04-28 |
| 9972124 | Elimination of minimal use threads via quad merging | Veynu Narasiman, Karthik Ramani | 2018-05-15 |
| 9760968 | Reduction of graphical processing through coverage testing | Michael C. Shebanow, Ignacio Llamas | 2017-09-12 |
| 9721376 | Elimination of minimal use threads via quad merging | Sang-oak Woo | 2017-08-01 |
| 8019975 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg +4 more | 2011-09-13 |
| 7941635 | High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2011-05-10 |
| 7941636 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 2011-05-10 |
| 7739482 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2010-06-15 |
| 7721070 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2010-05-18 |
| 7685402 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 2010-03-23 |
| 7657712 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 2010-02-02 |
| 7555631 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 2009-06-30 |
| 7555632 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2009-06-30 |
| 7487333 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2009-02-03 |
| 7162610 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2007-01-09 |
| 7028161 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2006-04-11 |
| 6986024 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2006-01-10 |
| 6965987 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg +4 more | 2005-11-15 |
| 6959375 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-10-25 |
| 6954844 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 2005-10-11 |