Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6948052 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-09-20 |
| 6941447 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-09-06 |
| 6934829 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-08-23 |
| 6915412 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-07-05 |
| 6647485 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2003-11-11 |
| 6611908 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 2003-08-26 |
| 6282630 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-28 |
| 6272579 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 2001-08-07 |
| 6272619 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-07 |
| 6256720 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-07-03 |
| 6249856 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Le Trong Nguyen, Sho Long Chen | 2001-06-19 |
| 6219763 | System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 2001-04-17 |
| 6128723 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-10-03 |
| 6101594 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-08-08 |
| 6092181 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-07-18 |
| 6047348 | System and method for supporting a multiple width memory subsystem | Cheng-Long Tang | 2000-04-04 |
| 6044449 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Le Trong Nguyen, Sho Long Chen | 2000-03-28 |
| 6038654 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 6038653 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 5961629 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1999-10-05 |
| 5941979 | Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1999-08-24 |
| 5886705 | Texture memory organization based on data locality | — | 1999-03-23 |
| 5887148 | System for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizes | Cheng-Long Tang | 1999-03-23 |
| 5838986 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 1998-11-17 |
| 5832292 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1998-11-03 |