Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7657712 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 2010-02-02 |
| 6954844 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 2005-10-11 |
| 6611908 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 2003-08-26 |
| 6272579 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 2001-08-07 |
| 6219763 | System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 2001-04-17 |
| 6047348 | System and method for supporting a multiple width memory subsystem | Derek J. Lentz | 2000-04-04 |
| 5941979 | Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 1999-08-24 |
| 5887148 | System for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizes | Derek J. Lentz | 1999-03-23 |
| 5828861 | System and method for reducing the critical path in memory control unit and input/output control unit operations | Yoshiyuki Miyayama | 1998-10-27 |
| 5754800 | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 1998-05-19 |
| 5604865 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 1997-02-18 |
| 5594877 | System for transferring data onto buses having different widths | Derek J. Lentz | 1997-01-14 |
| 5440752 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Le Trong Nguyen | 1995-08-08 |