Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5790134 | Hardware architecture for image generation and manipulation | — | 1998-08-04 |
| 5754800 | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1998-05-19 |
| 5689720 | High-performance superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1997-11-18 |
| 5682546 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 1997-10-28 |
| 5649173 | Hardware architecture for image generation and manipulation | — | 1997-07-15 |
| 5649230 | System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching | — | 1997-07-15 |
| 5604865 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1997-02-18 |
| 5594877 | System for transferring data onto buses having different widths | Cheng-Long Tang | 1997-01-14 |
| 5564117 | Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units | Johannes Wang, Trevor Deosaran, Linley M. Young, Kian-Chin Yap, Le Trong Nguyen +2 more | 1996-10-08 |
| 5561750 | Z-buffer tag memory organization | — | 1996-10-01 |
| 5560032 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-09-24 |
| 5559951 | Page printer controller including a single chip superscalar microprocessor with graphics functional units | Johannes Wang, Trevor Deosaran, Linley M. Young, Kian-Chin Yap, Le Trong Nguyen +2 more | 1996-09-24 |
| 5560035 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 1996-09-24 |
| 5539911 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-07-23 |
| 5533185 | Pixel modification unit for use as a functional unit in a superscalar microprocessor | Linley M. Young | 1996-07-02 |
| 5515494 | Graphics control planes for windowing and other display operations | — | 1996-05-07 |
| 5499384 | Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device | Kian-Chin Yap | 1996-03-12 |
| 5493687 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiv Garg, Le Trong Nguyen, Sho Long Chen | 1996-02-20 |
| 5481685 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1996-01-02 |
| 5448705 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1995-09-05 |
| 5446836 | Polygon rasterization | David R. Kosmal, Glenn Poole | 1995-08-29 |
| 5444853 | System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's | — | 1995-08-22 |
| 5440752 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1995-08-08 |
| 5440746 | System and method for synchronizing processors in a parallel processing environment | — | 1995-08-08 |
| 5428779 | System and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructions | Jean-Didier Allegrucci, Glenn Poole | 1995-06-27 |