Issued Patents All Time
Showing 26–50 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6941447 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-09-06 |
| 6934829 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-08-23 |
| 6915412 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2005-07-05 |
| 6782521 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Kevin R. Iadonato | 2004-08-24 |
| 6647485 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2003-11-11 |
| 6611908 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 2003-08-26 |
| 6425054 | Multiprocessor operation in a multimedia signal processor | — | 2002-07-23 |
| 6405273 | Data processing device with memory coupling unit | Rod G. Fleck, Klaus Oberlaender, Gigy Baror, Alfred Eder | 2002-06-11 |
| 6401232 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Kevin R. Iadonato | 2002-06-04 |
| 6401194 | Execution unit for processing a data stream independently and in parallel | Heonchul Park, Roney S. Wong, Ted T. Nguyen, Edward H. Yu | 2002-06-04 |
| 6289433 | Superscalar RISC instruction scheduling | Sanjiv Garg, Kevin R. Iadonato, Johannes Wang | 2001-09-11 |
| 6282630 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-28 |
| 6272619 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-07 |
| 6272579 | Microprocessor architecture capable of supporting multiple heterogeneous processors | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 2001-08-07 |
| 6263423 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Johannes Wang | 2001-07-17 |
| 6256720 | High performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-07-03 |
| 6249856 | RISC microprocessor architecture implementing multiple typed register sets | Sanjiy Garg, Derek J. Lentz, Sho Long Chen | 2001-06-19 |
| 6219763 | System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit | Derek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang | 2001-04-17 |
| 6192073 | Methods and apparatus for processing video data | Cliff Reader, Jae Cheol Son, Amjad Qureshi, Mark Frederiksen, Tim Lu | 2001-02-20 |
| 6173369 | Computer system for processing multiple requests and out of order returns using a request queue | Yasuaki Hagiwara | 2001-01-09 |
| 6173349 | Shared bus system with transaction and destination ID | Amjad Qureshi | 2001-01-09 |
| 6128723 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-10-03 |
| 6101594 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-08-08 |
| 6092181 | High-performance, superscalar-based computer system with out-of-order instruction execution | Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-07-18 |
| 6083274 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Kevin R. Iadonato | 2000-07-04 |