AQ

Amjad Qureshi

Samsung: 11 patents #12,136 of 75,807Top 20%
IBM: 2 patents #32,839 of 70,183Top 50%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
Overall (All Time): #275,822 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9640279 Apparatus and method for built-in test and repair of 3D-IC memory Donovan Scott Popps 2017-05-02
8090108 Secure debug interface and memory of a media security circuit and method Babu Chilukuri 2012-01-03
6816938 Method and apparatus for providing a modular system on-chip interface Sagar Edara, Ajit Deora, Ramana Kalapatapu 2004-11-09
6353867 Virtual component on-chip interface Ajit Deora, Ramana Kalapatapu, Sagar Edara 2002-03-05
6192073 Methods and apparatus for processing video data Cliff Reader, Jae Cheol Son, Le Trong Nguyen, Mark Frederiksen, Tim Lu 2001-02-20
6173349 Shared bus system with transaction and destination ID Le Trong Nguyen 2001-01-09
5983299 Priority request and bypass bus 1999-11-09
5982672 Simultaneous data transfer through read and write buffers of a DMA controller Kab Ju Moon 1999-11-09
5974480 DMA controller which receives size data for each DMA channel Kab Ju Moon, Le Trong Nguyen, Hoyoung Kim 1999-10-26
5974516 Byte-writable two-dimensional FIFO buffer having storage locations with fields indicating storage location availability and data ordering 1999-10-26
5918070 DMA controller with channel tagging Kab Ju Moon 1999-06-29
5898897 Bit stream signal feature detection in a signal processing system Jae Cheol Son 1999-04-27
5893168 Structure and method for memory initialization and power on Kab Ju Moon 1999-04-06
5835752 PCI interface synchronization Kevin Chiang 1998-11-10
5809537 Method and system for simultaneous processing of snoop and cache operations Randall C. Itskin, John C. Pescatore, David Brian Ruth 1998-09-15
5793776 Structure and method for SDRAM dynamic self refresh entry and exit using JTAG Sanghyeon Baeg 1998-08-11
5588010 Parallel architecture error correction and conversion system William R. Hardell, Jr. 1996-12-24