Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5896542 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 1999-04-20 |
| 5892963 | System and method for assigning tags to instructions to control instruction execution | Trevor Deosaran, Sanjiv Garg | 1999-04-06 |
| 5860000 | Floating point unit pipeline synchronized with processor pipeline | Prasenjit Biswas, Gautam Dewan, Norio Nakagawa, Kunio Uchiyama | 1999-01-12 |
| 5831871 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip | Le Trong Nguyen | 1998-11-03 |
| 5809276 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 1998-09-15 |
| 5737624 | Superscalar risc instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 1998-04-07 |
| 5734584 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Le Trong Nguyen | 1998-03-31 |
| 5628021 | System and method for assigning tags to control instruction processing in a superscalar processor | Trevor Deosaran, Sanjiv Garg | 1997-05-06 |
| 5604912 | System and method for assigning tags to instructions to control instruction execution | Trevor Deosaran, Sanjiv Garg | 1997-02-18 |
| 5590295 | System and method for register renaming | Trevor Deosaran, Sanjiv Garg | 1996-12-31 |
| 5566385 | Integrated structure layout and layout of interconnections for an integrated circuit chip | Le Trong Nguyen | 1996-10-15 |
| 5497499 | Superscalar risc instruction scheduling | Sanjiv Garg, Le Trong Nguyen, Johannes Wang | 1996-03-05 |
| 5371684 | Semiconductor floor plan for a register renaming circuit | Le Trong Nguyen | 1994-12-06 |