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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Prasenjit Biswas — 14 Patents

Intel: 6 patents #6,200 of 30,777Top 25%
HSHitachi Micro Systems: 3 patents #4 of 30Top 15%
CSCadence Design Systems: 2 patents #913 of 2,265Top 45%
HAHitachi America: 1 patents #46 of 97Top 50%
RARenesas Technology America: 1 patents #8 of 35Top 25%
SYSynopsys: 1 patents #1,143 of 2,302Top 50%
Saratoga, CA: #676 of 2,933 inventorsTop 25%
California: #43,920 of 386,348 inventorsTop 15%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Prasenjit Biswas has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in October 2023. Prasenjit Biswas ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Prasenjit Biswas in Saratoga, CA, US.

Patents per Year

Patents granted per year, 1999 to 2023Bar chart with a peak of 3 patents in 2007.peak 31999: 1 patents19992000: 1 patents2002: 1 patents20022004: 1 patents2007: 3 patents20072012: 1 patents2013: 1 patents20132014: 2 patents2015: 1 patents20152016: 1 patents2023: 1 patents2023

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11797742 Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design Diganchal Chakraborty, Jiri Prevratil, Harsh Chilwal, Shreedhar Ramachandra 2023-10-24 $64,758,000
9313491 Chroma motion vector processing apparatus, system, and method Yi-Jen Chiu, Mei-Chen Yeh, Louis A. Lippincott 2016-04-12 $10,096,000
9113151 Hardware accelerated compressed video bitstream escape code handling Musa Jahanghir, Adrian R. Pearson 2015-08-18 $11,320,000
8644392 Flexible macroblock ordering and arbitrary slice ordering apparatus, system, and method Yi-Jen Chiu 2014-02-04 $11,338,000
8630354 Hardware accelerated compressed video bitstream escape code handling Musa Jahanghir, Adrian R. Pearson 2014-01-14 $22,721,000
8379723 Chroma motion vector processing apparatus, system, and method Yi-Jen Chiu, Mei-Chen Yeh, Louis A. Lippincott 2013-02-19 $11,474,000
8126046 Flexible macroblock ordering and arbitrary slice ordering apparatus, system, and method Yi-Jen Chiu 2012-02-28 $20,590,000
7260792 Modeling a mixed-language mixed-signal design Chandrashekar L. Chetput, Ramesh S. Mayiladuthurai 2007-08-21 $25,510,000
7251795 Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design Ramesh S. Mayiladuthurai, Chandrashekar L. Chetput, Abhijeet Kolpekwar 2007-07-31 $11,423,000
7162616 Floating point unit pipeline synchronized with processor pipeline Gautam Dewan, Kevin R. Iadonato, Norio Nakagawa, Kunio Uchiyama 2007-01-09
6772327 Floating point unit pipeline synchronized with processor pipeline Gautam Dewan, Kevin R. Iadonato, Norio Nakagawa, Kunio Uchiyama 2004-08-03 $175,000
6418528 Floating point unit pipeline synchronized with processor pipeline Gautam Dewan, Kevin R. Iadonato, Norio Nakagawa, Kunio Uchiyama 2002-07-09 $326,000
6012139 Microprocessor including floating point unit with 16-bit fixed length instruction set Shumpei Kawasaki, Norio Nakagawa, Osamu Nishii, Kunio Uchiyama 2000-01-04 $1,488,000
5860000 Floating point unit pipeline synchronized with processor pipeline Gautam Dewan, Kevin R. Iadonato, Norio Nakagawa, Kunio Uchiyama 1999-01-12 $279,000