Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7877572 | Data access in a processor for virtual machines | Toshiyasu Morita | 2011-01-25 |
| 7412581 | Processor for virtual machines and method therefor | Toshiyasu Morita | 2008-08-12 |
| 6996700 | Microcomputer and dividing circuit | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2006-02-07 |
| 6845908 | Storage card with integral file system, access control and cryptographic support | Toshiyasu Morita | 2005-01-25 |
| 6748507 | Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2004-06-08 |
| 6735683 | Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2004-05-11 |
| 6591294 | Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2003-07-08 |
| 6343357 | Microcomputer and dividing circuit | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2002-01-29 |
| 6324634 | Methods for operating logical cache memory storing logical and physical address information | Shinichi Yoshioka | 2001-11-27 |
| 6279063 | Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2001-08-21 |
| 6272620 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2001-08-07 |
| 6253308 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2001-06-26 |
| 6223265 | Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2001-04-24 |
| 6212620 | Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 2001-04-03 |
| 6205535 | Branch instruction having different field lengths for unconditional and conditional displacements | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2001-03-20 |
| 6138226 | Logical cache memory storing logical and physical address information for resolving synonym problems | Shinichi Yoshioka | 2000-10-24 |
| 6131154 | Microcomputer having variable bit width area for displacement | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2000-10-10 |
| 6122724 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 2000-09-19 |
| 6012139 | Microprocessor including floating point unit with 16-bit fixed length instruction set | Prasenjit Biswas, Norio Nakagawa, Osamu Nishii, Kunio Uchiyama | 2000-01-04 |
| 5991545 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 1999-11-23 |
| 5987589 | Microcomputer and microcomputer system | Kaoru Fukada, Mitsuru Watabe, Kouki Noguchi, Kiyoshi Matsubara, Isamu Mochizuki +4 more | 1999-11-16 |
| 5969976 | Division circuit and the division method thereof | Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba +15 more | 1999-10-19 |
| 5930833 | Logical cache memory storing logical and physical address information for resolving synonym problems | Shinichi Yoshioka | 1999-07-27 |
| 5930523 | Microcomputer having multiple bus structure coupling CPU to other processing elements | Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu +3 more | 1999-07-27 |
| 5832248 | Semiconductor integrated circuit having CPU and multiplier | Kazumasa Kishi, Shigeki Masumura, Hideo Nakamura, Kouki Noguchi, Yasushi Akao | 1998-11-03 |