HO

Hiroshi Ohsuga

HI Hitachi: 11 patents #3,813 of 28,497Top 15%
HE Hitachi Vlsi Engineering: 3 patents #237 of 666Top 40%
RT Renesas Technology: 2 patents #1,374 of 3,337Top 45%
Overall (All Time): #387,376 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7558944 Microcomputer Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 2009-07-07
7363466 Microcomputer Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 2008-04-22
7069423 Microcomputer Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 2006-06-27
6748507 Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2004-06-08
6735683 Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2004-05-11
6591294 Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2003-07-08
6434690 Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 2002-08-13
6405302 Microcomputer Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 2002-06-11
6279063 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2001-08-21
6223265 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2001-04-24
6212620 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 2001-04-03
5930523 Microcomputer having multiple bus structure coupling CPU to other processing elements Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Keiichi Kurakazu +3 more 1999-07-27
5867726 Microcomputer Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao +1 more 1999-02-02