Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6996700 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2006-02-07 |
| 6748507 | Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2004-06-08 |
| 6735683 | Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2004-05-11 |
| 6591294 | Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2003-07-08 |
| 6351788 | Data processor and data processing system | Takanaga Yamazaki, Yasushi Akao, Masayasu Ohizumi, Takeshi Kataoka, Tatsuo Nakai +2 more | 2002-02-26 |
| 6343357 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2002-01-29 |
| 6279063 | Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-08-21 |
| 6272620 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-08-07 |
| 6253308 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-06-26 |
| 6223265 | Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-04-24 |
| 6212620 | Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-04-03 |
| 6205535 | Branch instruction having different field lengths for unconditional and conditional displacements | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-03-20 |
| 6131154 | Microcomputer having variable bit width area for displacement | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-10-10 |
| 6122724 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-09-19 |
| 5991545 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-11-23 |
| 5969976 | Division circuit and the division method thereof | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-10-19 |
| 5930523 | Microcomputer having multiple bus structure coupling CPU to other processing elements | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 1999-07-27 |
| 5682545 | Microcomputer having 16 bit fixed length instruction format | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1997-10-28 |
| 5644703 | Data processor providing fast break in program execution | Yoshikazu Aoto, Shiro Baba, Satoshi Masuda, Hiroyuki Kida, Shinji Kawashima +1 more | 1997-07-01 |
| 5517664 | RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing | Tan Watanabe, Yugo Kashiwagi, Keisuke Toyama, Tohru Nojiri | 1996-05-14 |
| 5493659 | Data processor providing fast break in program execution | Yoshikazu Aoto, Shiro Baba, Satoshi Masuda, Hiroyuki Kida, Shinji Kawashima +1 more | 1996-02-20 |
| 5450610 | RISC system capable of performing calls and returns without advancing or restoring window pointers | Tan Watanabe, Yugo Kashiwagi, Keisuke Toyama, Thoru Nojiri | 1995-09-12 |
| 5375211 | Bus error processing system having direct bus master/CPU communication | Takashi Maruyama, Susumu Kaneko, Hiroyuki Kida | 1994-12-20 |
| 5307502 | Data processing system having multiple register management for call and return operations | Tan Watanabe, Yugo Kashiwagi, Keisuke Toyama, Tohru Nojiri | 1994-04-26 |
| 5305460 | Data processor | Susumu Kaneko | 1994-04-19 |