Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6996700 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2006-02-07 |
| 6343357 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2002-01-29 |
| 6272620 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-08-07 |
| 6253308 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-06-26 |
| 6205535 | Branch instruction having different field lengths for unconditional and conditional displacements | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-03-20 |
| 6131154 | Microcomputer having variable bit width area for displacement | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-10-10 |
| 6122724 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-09-19 |
| 5991545 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-11-23 |
| 5969976 | Division circuit and the division method thereof | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-10-19 |
| 5956263 | Multiplication, division and square root extraction apparatus | Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida +5 more | 1999-09-21 |
| 5682545 | Microcomputer having 16 bit fixed length instruction format | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1997-10-28 |
| 5631858 | System for obtaining strict solution in accordance with accuracy of approximate solutions | Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida +5 more | 1997-05-20 |
| 5632024 | Microcomputer executing compressed program and generating compressed branch addresses | Hiroshi Yajima | 1997-05-20 |
| 5517664 | RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing | Tan Watanabe, Keiichi Kurakazu, Keisuke Toyama, Tohru Nojiri | 1996-05-14 |
| 5515519 | Data processor and method utilizing coded no-operation instructions | Shinichi Yoshioka, Fumio Arakawa, Hiroshi Yajima | 1996-05-07 |
| 5450610 | RISC system capable of performing calls and returns without advancing or restoring window pointers | Tan Watanabe, Keiichi Kurakazu, Keisuke Toyama, Thoru Nojiri | 1995-09-12 |
| 5307502 | Data processing system having multiple register management for call and return operations | Tan Watanabe, Keiichi Kurakazu, Keisuke Toyama, Tohru Nojiri | 1994-04-26 |
| 5293558 | Multiplication, division and square root extraction apparatus | Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida +5 more | 1994-03-08 |
| 5214786 | RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled | Tan Watanabe, Keiichi Kurakazu, Keisuke Toyama, Thoru Nojiri | 1993-05-25 |