ON

Osamu Nishii

HI Hitachi: 27 patents #1,104 of 28,497Top 4%
RT Renesas Technology: 11 patents #212 of 3,337Top 7%
RE Renesas Electronics: 7 patents #554 of 4,529Top 15%
HE Hitachi Vlsi Engineering: 3 patents #237 of 666Top 40%
HC Hitachi Ulsi Systems Co.: 2 patents #419 of 867Top 50%
HS Hitachi Micro Systems: 1 patents #13 of 30Top 45%
Overall (All Time): #63,324 of 4,157,543Top 2%
46
Patents All Time

Issued Patents All Time

Showing 1–25 of 46 patents

Patent #TitleCo-InventorsDate
10365979 Lockstepped CPU selection based on failure status Kiwamu Takada 2019-07-30
9734023 Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information Kiwamu Takada 2017-08-15
8364988 Substrate bias switching unit for a low power processor Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Kunio Uchiyama, Takanori Shimura +3 more 2013-01-29
8234441 Processor system using synchronous dynamic memory Kunio Uchiyama 2012-07-31
8145889 Data processing system with branch target addressing using upper and lower bit permutation 2012-03-27
7958379 Substrate bias switching unit for a low power processor Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Kunio Uchiyama, Takanori Shimura +3 more 2011-06-07
7904641 Processor system using synchronous dynamic memory Kunio Uchiyama 2011-03-08
7836286 Data processing system to calculate indexes into a branch target address table based on a current operating mode 2010-11-16
RE41589 Memory system performing fast access to a memory location by omitting the transfer of a redundant address Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda 2010-08-24
7475261 Substrate bias switching unit for a low power processor Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Kunio Uchiyama, Takanori Shimura +3 more 2009-01-06
7376783 Processor system using synchronous dynamic memory Kunio Uchiyama 2008-05-20
7254082 Semiconductor device Takao Watanabe, Kunio Uchiyama, Naohiko Irie, Hiroyuki Mizuno 2007-08-07
7178046 Halting clock signals to input and result latches in processing path upon fetching of instruction not supported Tetsuya Yamada, Tomoichi Hayashi, Sadaki Nakano, Takanobu Tsunoda 2007-02-13
7143230 Processor system using synchronous dynamic memory Kunio Uchiyama 2006-11-28
7023757 Semiconductor device Takao Watanabe, Kunio Uchiyama, Naohiko Irie, Hiroyuki Mizuno 2006-04-04
7003651 Program counter (PC) relative addressing mode with fast displacement Yuki Kondoh 2006-02-21
6879188 Semiconductor integrated circuit device Masayuki Miyazaki, Ken Tatezawa, Kiwamu Takada, Kunio Uchiyama, Kiyoshi Hasegawa +2 more 2005-04-12
6877087 Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving Tetsuya Yamada, Tomoichi Hayashi, Sadaki Nakano, Takanobu Tsunoda 2005-04-05
6715090 Processor for controlling substrate biases in accordance to the operation modes of the processor Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Kunio Uchiyama, Takanori Shimura +3 more 2004-03-30
6697908 Processor system using synchronous dynamic memory Kunio Uchiyama 2004-02-24
6654305 System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit Takanobu Tsunoda 2003-11-25
6604202 Low power processor Masayuki Miyazaki, Kiyoo Itoh 2003-08-05
6532528 Data processor and data processor system having multiple modes of address indexing and operation Junichi Nishimoto, Fumio Arakawa, Susumu Narita, Masayuki Ito, Makoto Toda +1 more 2003-03-11
6515519 Semiconductor integrated circuit device Masayuki Miyazaki, Ken Tatezawa, Kiwamu Takada, Kunio Uchiyama, Kiyoshi Hasegawa +2 more 2003-02-04
6493255 Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device Motonobu Tonomura, Takanobu Tsunoda 2002-12-10