Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6424560 | Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device | Motonobu Tonomura, Takanobu Tsunoda | 2002-07-23 |
| 6334166 | Processor system using synchronous dynamic memory | Kunio Uchiyama | 2001-12-25 |
| 6292867 | Data processing system | Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda | 2001-09-18 |
| 6260107 | Processor system using synchronous dynamic memory | Kunio Uchiyama | 2001-07-10 |
| 6154807 | Memory system performing fast access to a memory location by omitting the transfer of a redundant address | Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda | 2000-11-28 |
| 6092172 | Data processor and data processing system having two translation lookaside buffers | Junichi Nishimoto, Fumio Arakawa, Susumu Narita, Masayuki Ito, Makoto Toda +1 more | 2000-07-18 |
| 6078983 | Multiprocessor system having distinct data bus and address bus arbiters | Makoto Hanawa, Tadahiko Nishimukai, Makoto Suzuki | 2000-06-20 |
| 6078986 | Processor system using synchronous dynamic memory | Kunio Uchiyama | 2000-06-20 |
| 6012139 | Microprocessor including floating point unit with 16-bit fixed length instruction set | Prasenjit Biswas, Shumpei Kawasaki, Norio Nakagawa, Kunio Uchiyama | 2000-01-04 |
| 5918045 | Data processor and data processing system | Sadaki Nakano, Norio Nakagawa, Takanobu Tsunoda | 1999-06-29 |
| 5873122 | Memory system performing fast access to a memory location by omitting transfer of a redundant address | Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda | 1999-02-16 |
| 5740401 | Multiprocessor system having a processor invalidating operand cache when lock-accessing | Makoto Hanawa, Tadahiko Nishimukai, Makoto Suzuki | 1998-04-14 |
| 5652858 | Method for prefetching pointer-type data structure and information processing apparatus therefor | Tetsuhiko Okada, Hiroshi Takeda | 1997-07-29 |
| 5574876 | Processor system using synchronous dynamic memory | Kunio Uchiyama | 1996-11-12 |
| 5557760 | Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus | Takashi Inagawa, Makoto Hanawa, Hiroshi Takeda | 1996-09-17 |
| 5375215 | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank | Makoto Hanawa, Tadahiko Nishimukai, Makoto Suzuki | 1994-12-20 |
| 5301285 | Data processor having two instruction registers connected in cascade and two instruction decoders | Makoto Hanawa, Susumu Narita, Kunio Uchiyama | 1994-04-05 |
| 5287484 | Multi-processor system for invalidating hierarchical cache | Kunio Uchiyama, Hirokazu Aoki, Takashi Kikuchi, Yasuhiko Saigou | 1994-02-15 |
| 5283886 | Multiprocessor cache system having three states for generating invalidating signals upon write accesses | Kunio Uchiyama, Hirokazu Aoki, Kanji Oishi, Jun Kitano, Susumu Hatano | 1994-02-01 |
| 5267198 | Static memory containing sense amp and sense amp switching circuit | Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta +2 more | 1993-11-30 |
| 5193075 | Static memory containing sense AMP and sense AMP switching circuit | Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta +2 more | 1993-03-09 |