Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Sadaki Nakano — 11 Patents

Hitachi: 8 patents #5,193 of 28,497Top 20%
RTRenesas Technology: 3 patents #990 of 3,337Top 30%
Kokubunji, JP: #176 of 714 inventorsTop 25%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Sadaki Nakano has been granted 11 US patents while listed as an inventor at Hitachi. The first was granted in 1999 and the most recent in November 2022. Sadaki Nakano ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Sadaki Nakano in Kokubunji, JP.

Patents per Year

Patents granted per year, 1999 to 2022Bar chart with a peak of 3 patents in 2007.peak 31999: 1 patents19992005: 2 patents20052007: 3 patents20072008: 1 patents20082014: 1 patents20142016: 1 patents20162022: 2 patents2022

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11495026 Aerial line extraction system and method Nobutaka KIMURA, Kishiko Maruyama, Nobuhiro Chihara 2022-11-08
11295130 Aerial line extraction system and aerial line extraction method Kishiko Maruyama, Nobutaka KIMURA 2022-04-05
9270518 Computer system and rule generation method Keiro Muro 2016-02-23
8898189 Database management method, computer, sensor network system and time-series data management method Keiro Muro, Shinji Fujiwara 2014-11-25
7345590 Wireless terminal with gas leakage detection function, gas leakage detection system using the same, and gas leakage notification method Koichi Yokosawa, Yasushi Goto 2008-03-18 $190,000
7242309 Gas detection system Koichi Yokosawa, Yasushi Goto 2007-07-10 $198,000
7187961 Semiconductor device for sensor system Shunzo Yamashita, Kei Suzuki, Toshiyuki Aritsuka, Masayuki Miyazaki 2007-03-06 $264,000
7178046 Halting clock signals to input and result latches in processing path upon fetching of instruction not supported Tetsuya Yamada, Tomoichi Hayashi, Takanobu Tsunoda, Osamu Nishii 2007-02-13 $171,000
6950767 Quality monitoring system for building structure, quality monitoring method for building structure and semiconductor integrated circuit device Shunzo Yamashita, Kei Suzuki, Toshiyuki Aritsuka 2005-09-27 $99,000
6877087 Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving Tetsuya Yamada, Tomoichi Hayashi, Takanobu Tsunoda, Osamu Nishii 2005-04-05 $81,000
5918045 Data processor and data processing system Osamu Nishii, Norio Nakagawa, Takanobu Tsunoda 1999-06-29 $691,000