Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7451491 | Method and a device for allowing only a specific kind of hardware to correctly execute software | Momoto Watanabe, Hiroaki Sano | 2008-11-11 |
| 6779102 | Data processor capable of executing an instruction that makes a cache memory ineffective | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 2004-08-17 |
| 6476644 | Clocked logic gate circuit | Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko +1 more | 2002-11-05 |
| 6333645 | Clocked logic gate circuit | Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko +1 more | 2001-12-25 |
| 6316961 | Clocked logic gate circuit | Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko +1 more | 2001-11-13 |
| 6282505 | Multi-port memory and a data processor accessing the same | Kenji Kaneko, Kazumichi Yamamoto, Kentaro Shimada | 2001-08-28 |
| 6272596 | Data processor | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 2001-08-07 |
| 6078983 | Multiprocessor system having distinct data bus and address bus arbiters | Tadahiko Nishimukai, Osamu Nishii, Makoto Suzuki | 2000-06-20 |
| 6052776 | Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition | Yoshio Miki, Kentaro Shimada | 2000-04-18 |
| 5974533 | Data processor | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 1999-10-26 |
| 5881078 | Logic circuit having error detection function and processor including the logic circuit | Yoshio Miki, Tatsuya Kawashimo | 1999-03-09 |
| 5878254 | Instruction branching method and a processor | Kentaro Shimada, Kazumichi Yamamoto, Kenji Kaneko | 1999-03-02 |
| 5809274 | Purge control for ON-chip cache memory | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 1998-09-15 |
| 5790845 | System with reservation instruction execution to store branch target address for use upon reaching the branch point | Kentaro Shimada, Kazumichi Yamamoto, Kenji Kaneko | 1998-08-04 |
| 5740401 | Multiprocessor system having a processor invalidating operand cache when lock-accessing | Tadahiko Nishimukai, Osamu Nishii, Makoto Suzuki | 1998-04-14 |
| 5680631 | Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 1997-10-21 |
| 5654651 | CMOS static logic circuit | Kenji Kaneko, Kentaro Shimada, Kazunori Nakajima | 1997-08-05 |
| 5572151 | Pass transistor type selector circuit and digital logic circuit | Kenji Kaneko, Noriyasu Ido | 1996-11-05 |
| 5557760 | Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus | Osamu Nishii, Takashi Inagawa, Hiroshi Takeda | 1996-09-17 |
| 5386394 | Semiconductor memory device for performing parallel operations on hierarchical data lines | Takayuki Kawahara, Masakazu Aoki, Yoshinobu Nakagome, Kunio Uchiyama, Masayuki Nakamura +2 more | 1995-01-31 |
| 5381531 | Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction | Tadahiko Nishimukai, Makoto Suzuki, Katsuhiro Shimohigashi | 1995-01-10 |
| 5375215 | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank | Tadahiko Nishimukai, Osamu Nishii, Makoto Suzuki | 1994-12-20 |
| 5349672 | Data processor having logical address memories and purge capabilities | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki | 1994-09-20 |
| 5301285 | Data processor having two instruction registers connected in cascade and two instruction decoders | Osamu Nishii, Susumu Narita, Kunio Uchiyama | 1994-04-05 |
| 5269007 | RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register | Tadahiko Nishimukai | 1993-12-07 |