Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6779102 | Data processor capable of executing an instruction that makes a cache memory ineffective | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 2004-08-17 |
| 6381680 | Data processing system with an enhanced cache memory control | Atsushi Hasegawa, Masaru Matsumura | 2002-04-30 |
| 6272596 | Data processor | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 2001-08-07 |
| 6078983 | Multiprocessor system having distinct data bus and address bus arbiters | Makoto Hanawa, Osamu Nishii, Makoto Suzuki | 2000-06-20 |
| 5974533 | Data processor | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1999-10-26 |
| 5822761 | Data processing system which controls operation of cache memory based and the address being accessed | Atsushi Hasegawa, Masaru Matsumura | 1998-10-13 |
| 5809274 | Purge control for ON-chip cache memory | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1998-09-15 |
| 5740401 | Multiprocessor system having a processor invalidating operand cache when lock-accessing | Makoto Hanawa, Osamu Nishii, Makoto Suzuki | 1998-04-14 |
| 5680631 | Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1997-10-21 |
| 5619677 | Data processing system with an enhanced cache memory control | Atsushi Hasegawa, Masaru Matsumura | 1997-04-08 |
| 5509133 | Data processing system with an enhanced cache memory control | Atsushi Hasegawa, Masaru Matsumura | 1996-04-16 |
| 5502825 | Data processing system with an enhanced cache memory control | Atsushi Hasegawa, Masaru Matsumura | 1996-03-26 |
| 5479625 | Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays | Atsushi Hasegawa, Masaru Matsumura | 1995-12-26 |
| 5442229 | Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly | Takao Mori, Satoshi Yoshida, Kenji Yamaguchi | 1995-08-15 |
| 5430397 | Intra-LSI clock distribution circuit | Hiroyuki Itoh, Noboru Masuda, Hideo Maejima | 1995-07-04 |
| 5381531 | Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction | Makoto Hanawa, Makoto Suzuki, Katsuhiro Shimohigashi | 1995-01-10 |
| 5375215 | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank | Makoto Hanawa, Osamu Nishii, Makoto Suzuki | 1994-12-20 |
| 5349672 | Data processor having logical address memories and purge capabilities | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1994-09-20 |
| 5269007 | RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register | Makoto Hanawa | 1993-12-07 |
| 5253197 | Semiconductor associative memory device with current sensing | Makoto Suzuki, Suguru Tachibana, Hisayuki Higuchi, Katsuhiro Shimohigashi, Takehisa Hayashi +1 more | 1993-10-12 |
| 5206945 | Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1993-04-27 |
| 5202969 | Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively | Katsuyuki Sato, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi +3 more | 1993-04-13 |
| 5165086 | Microprocessor chip using two-level metal lines technology | Shigehiro Kamejima, Yoshimune Hagiwara, Kouki Noguchi, Minoru Ishii, Hideo Nakamura +2 more | 1992-11-17 |
| 5148526 | Data processing system with an enhanced cache memory control | Atsushi Hasegawa, Masaru Matsumura | 1992-09-15 |
| 5148532 | Pipeline processor with prefetch circuit | Susumu Narita, Makoto Hanawa, Tetsuhiko Okada | 1992-09-15 |