Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5146573 | Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register | Katsuyuki Sato, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi +3 more | 1992-09-08 |
| 5129075 | Data processor with on-chip logical addressing and off-chip physical addressing | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1992-07-07 |
| 4989140 | Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit | Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa | 1991-01-29 |
| 4942521 | Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable | Makoto Hanawa, Atsushi Hasegawa | 1990-07-17 |
| 4937738 | Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction | Kunio Uchiyama, Atsushi Hasegawa, Takeshi Aimoto | 1990-06-26 |
| 4912635 | System for reexecuting branch instruction without fetching by storing target instruction control information | Atsushi Hasegawa, Kunio Uchiyama, Yoshifumi Takamoto | 1990-03-27 |
| 4845614 | Microprocessor for retrying data transfer | Makoto Hanawa, Ikuya Kawasaki | 1989-07-04 |
| 4803616 | Buffer memory | Kunio Uchiyama, Atsushi Hasegawa | 1989-02-07 |
| 4797816 | Virtual memory supported processor having restoration circuit for register recovering | Kunio Uchiyama | 1989-01-10 |
| 4720811 | Microprocessor capable of stopping its operation at any cycle time | Noboru Yamaguchi, Kunio Uchiyama, Haruo Koizumi, Yoshimune Hagiwara | 1988-01-19 |
| 4646271 | Content addressable memory having dual access modes | Kunio Uchiyama | 1987-02-24 |