Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7100055 | Information storage system, information transfer system and storage medium thereof | Toru Owada, Jun Kitahara, Takeshi Asahi, Takayuki Tamura, Nagamasa Mizushima +1 more | 2006-08-29 |
| 6810454 | Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system | Nobukazu Kondo, Koki Noguchi | 2004-10-26 |
| 6792493 | Data processing system having a card type interface with assigned addressing | Shigezumi Matsui, Susumu Narita, Masato Nemoto | 2004-09-14 |
| 6779102 | Data processor capable of executing an instruction that makes a cache memory ineffective | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 2004-08-17 |
| 6708304 | Semiconductor device | Akifumi Tsukimori, Shinichi Yoshioka, Koki Noguchi | 2004-03-16 |
| 6665807 | Information processing apparatus | Nobukazu Kondo, Koki Noguchi | 2003-12-16 |
| 6594720 | Data processing system having a PC card type interface with assigned addressing | Shigezumi Matsui, Susumu Narita, Masato Nemoto | 2003-07-15 |
| 6539444 | Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system | Nobukazu Kondo, Koki Noguchi | 2003-03-25 |
| 6425039 | Accessing exception handlers without translating the address | Shinichi Yoshioka, Shigezumi Matsui, Susumu Narita | 2002-07-23 |
| 6272596 | Data processor | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 2001-08-07 |
| 6049844 | Microprocessor having a PC card type interface | Shigezumi Matsui, Susumu Narita, Masato Nemoto | 2000-04-11 |
| 6047354 | Data processor for implementing virtual pages using a cache and register | Shinichi Yoshioka, Susumu Narita, Saneaki Tamaki | 2000-04-04 |
| 6038661 | Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler | Shinichi Yoshioka, Shigezumi Matsui, Susumu Narita | 2000-03-14 |
| 5974533 | Data processor | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 1999-10-26 |
| 5907867 | Translation lookaside buffer supporting multiple page sizes | Toshinobu Shinbo, Suguru Tachibana, Susumu Narita, Shinichi Yoshioka, Koichiro Ishibashi +3 more | 1999-05-25 |
| 5848247 | Microprocessor having PC card interface | Shigezumi Matsui, Susumu Narita, Masato Nemoto | 1998-12-08 |
| 5835963 | Processor with an addressable address translation buffer operative in associative and non-associative modes | Shinichi Yoshioka, Susumu Narita, Saneaki Tamaki | 1998-11-10 |
| 5809274 | Purge control for ON-chip cache memory | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 1998-09-15 |
| 5796978 | Data processor having an address translation buffer operable with variable page sizes | Shinichi Yoshioka, Susumu Narita, Saneaki Tamaki | 1998-08-18 |
| 5778237 | Data processor and single-chip microcomputer with changing clock frequency and operating voltage | Mitsuyoshi Yamamoto, Hideo Inayoshi, Susumu Narita, Masaharu Kubo | 1998-07-07 |
| 5774701 | Microprocessor operating at high and low clok frequencies | Shigezumi Matsui, Mitsuyoshi Yamamoto, Shinichi Yoshioka, Susumu Narita, Susumu Kaneko +1 more | 1998-06-30 |
| 5680631 | Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 1997-10-21 |
| 5564041 | Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation | Shigezumi Matsui, Yoshiyuki Kondo, Kouji Hashimoto | 1996-10-08 |
| 5398319 | Microprocessor having apparatus for dynamically controlling a kind of operation to be performed by instructions to be executed | Ken Sakamura, Atsushi Hasegawa, Kazuhiko Iwasaki, Motonobu Tonomura | 1995-03-14 |
| 5349672 | Data processor having logical address memories and purge capabilities | Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Makoto Hanawa | 1994-09-20 |