Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8484448 | Information processing device | Motokazu Ozawa, Naohiko Irie, Hisayoshi Ide, Miki Hayakawa | 2013-07-09 |
| 8122233 | Information processing device | Motokazu Ozawa, Naohiko Irie, Hisayoshi Ide, Miki Hayakawa | 2012-02-21 |
| 7774017 | Semiconductor integrated circuit device | Takahiro Irita, Kunihiko Nishiyama, Takao Koike, Koji Goto, Masayuki Ito | 2010-08-10 |
| 7380149 | Information processing device | Motokazu Ozawa, Naohiko Irie, Hisayoshi Ide, Miki Hayakawa | 2008-05-27 |
| 7286386 | Semiconductor device | Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato +3 more | 2007-10-23 |
| 7061785 | Stacked large-scale integrated circuit (LSI) semiconductor device with miniaturization and thinning of package | Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato +3 more | 2006-06-13 |
| 6047354 | Data processor for implementing virtual pages using a cache and register | Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita | 2000-04-04 |
| 5907867 | Translation lookaside buffer supporting multiple page sizes | Toshinobu Shinbo, Suguru Tachibana, Susumu Narita, Shinichi Yoshioka, Koichiro Ishibashi +3 more | 1999-05-25 |
| 5835963 | Processor with an addressable address translation buffer operative in associative and non-associative modes | Shinichi Yoshioka, Susumu Narita, Ikuya Kawasaki | 1998-11-10 |
| 5796978 | Data processor having an address translation buffer operable with variable page sizes | Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita | 1998-08-18 |